Tag Archives: PAPER

Improving the key parameters of each analog block is mandatory to push the performance of a data converter to the technology limit.  Lorenzo Scaletti has presented our last work “A Novel Push-Pull Input Buffer for Wideband ADCs with improved High-Frequency … Continue reading →

Gabriele Be’ will be presenting the paper “A 900-MS/S SAR-Based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations”, at the IEEE MWSCAS 2022. The extended version of this paper was also published in the journal Transactions on Circuits and Systems II . This work was possible thanks to the collaboration of … Continue reading →

Luca Ricci will be presenting the paper “Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs”, at the next IEEE ISCAS 2022. [URL]

Lorenzo Scaletti will be presenting the paper “A 10.2-ENOB, 150-MS/s Redundant SAR ADC with a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters”, at the next IEEE NEWCAS 2022. [URL]

Francesco Buccoleri will be presenting the paper “A 9GHz 72fs-Total-Integrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler”, at the next IEEE Custom Integrated Circuits Conference (CICC). This work was possible thanks to the collaboration of Politecnico di Milano with Infineon … Continue reading →

Simone Dartizio will be presenting the paper “A 68.6-fs-rms-Total-Integrated-Jitter and 1.56-us-Locking-Time Fractional-N Bang-Bang PLL Based on a Type-II Gear Shifting and Adaptive Frequency Switching” at the next IEEE International Solid-State Circuits Conference (ISSCC). This work was possible thanks to the … Continue reading →