Tag Archives: IEEE

In high-performance fractional-N frequency synthesizers, fractional spurs are a critical bottleneck—especially at near-integer channels—degrading both jitter and spectral purity. With next-generation wireless transceivers targeting extremely low jitter (below 80fs), effective spur mitigation becomes essential, often requiring suppression below –60 dBc. In … Continue reading →

We are pleased to share that two of our PhD students presented their research at the VLSI Symposium 2025 in Kyoto. Michele Rossoni presented “A Fractional-N Digital-PLL based on a Power-Gated Ring-Oscillator and a Frequency-Stabilizing Loop Achieving 74fs Jitter Under … Continue reading →

Low jitter frequency synthesizers are required to achieve high data-rates in modern wireless and wireline transceivers. When battery powered devices utilize these synthesizers their power consumption must be limited, leading to complex design challenges. In our latest article we unveil … Continue reading →

We’re delighted to announce our involvement in the recent CICC event held in Denver. Our research team showcased two significant contributions: Pietro Salvi presented the work “A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC” Michele Rossoni introduced “A … Continue reading →

ARPLab has just received the ISSCC 2023 Jan Van Vessem Award for Oustanding European Paper for the paper “A 76.7fs-Integrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.” The paper introduced a … Continue reading →