New Publication – VLSI24

We are proud to announce that today, June 20 at 4:15 pm (HST), Riccardo Moleri will be presenting our research work titled “A 79.3fs Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique” at the 2024 VLSI Symposium on Technology and Circuits in Honolulu, Hawaii.

Thanks to the entire ARPLab PLL team and Infineon Technologies, Villach, for making it possible!

We look forward to meeting you all in the Honolulu 2 conference room!

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Staff – New Job Positions

Alessandro Dago, Francesco Buccoleri e Lorenzo Scaletti have moved respectively to Allegro Microsystems (Assago, Italy), Kandou (Lausanne, Switzerland) and Infienon Technologies (Villach, Austria). Good luck Alessandro, Francesco e Lorenzo and thank you for your hard work and contribution to the lab!

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New Publications – CICC24

We’re delighted to announce our involvement in the recent CICC event held in Denver. Our research team showcased two significant contributions:

Pietro Salvi presented the work “A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC”

Michele Rossoni introduced “A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector”

Congratulations to the ARPLab PLL research Team for these remarkable accomplishments

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New Publications – APEC24

Our team has just wrapped up an insightful journey at the Applied Power Electronics Conference (APEC 2024), showcasing three papers. APEC stands as the premier conference in the realm of medium-low power conversion applications (<1kW). Huge congratulations to Paolo Melillo and Simone Zaffin for their outstanding presentations, earning them the best presentation awards in their respective sessions!

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New Award – ISSCC 2023

ARPLab has just received the ISSCC 2023 Jan Van Vessem Award for Oustanding European Paper for the paper “A 76.7fs-Integrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.”

The paper introduced a new concept to design linear digital-to-time converters, the “Inverse-Constant-Slope DTC”, that is crucial for achieving beyond state-of-the-art performance in frequency synthesizers. The PLL prototype was developed in the ARPLab laboratory at the Department of Electronics, Information and Bioengineering, Politecnico di Milano and manufactured using a 28nm CMOS TSMC technology. The results concretely demonstrate the feasibility of bang-bang PLLs for high-performance wireless applications.

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New Publications – ISSCC24

In the upcoming 71st IEEE International Solid-State Circuits Conference (ISSCC) scheduled for February, our laboratory is pleased to announce its participation with three contributions:

In Session number 10 (Frequency Synthesis):

Michele Rossoni will be presenting the paper “An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fs rms Integrated Jitter and -252.4dB FoM”.

Francesco Tesolin will be presenting the paper “A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion”.

In the framework of the Student-Research Preview, Pietro Salvi will be presenting the poster “A 66.7fs-Integrated-Jitter Bang-Bang Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC”.

Congratulations to the ARPLab PLL research Team for these achievements, made also possibile thanks to the contribution of Infineon Technologies, Villach

Hope to see you in San Francisco!

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Circuit Technology Symposium at The Seoul National University

Earlier this month, our PhD candidate Michele Rossoni visited Seoul National University, where he met with students from Professor Jaehyouk Choi’s research laboratory on RF electronics.

It was a pleasure to meet other researchers working in our same field, share technical discussions, and present our latest work.

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New Publication – ICECS23 & TCAS II

We are proud to announce that our PhD candidate Gabriele Zanoletti has presented our last work: “A 250-MS/s 9.9-ENOB 80.7dB-SFDR Top-Plate Input SAR ADC with Charge Linearization” at the 2023 International Conference on Electronics, Circuits and Systems (ICECS), Istanbul, Turkey.

The paper was also selected for publication in the IEEE Transactions on Circuits and Systems II and it is available in early access.

Congratulations to the ARPLab ADC research Team for the achievement.
This work was made possible thanks to the collaboration of Politecnico di Milano with Infineon Technologies, Villach.

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New Publication – PRIME23

Paolo Melillo and Simone Zaffin presented their two papers at the 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), held in Valencia, Spain in June 2023. Paolo Melillo was also the recipient of the silver leaf award, the certificate reserved only for the top 20% papers. Congratulations to the ARPLab Power research Team for all these achievements. This work was possible thanks to the collaboration of Politecnico di Milano with STMicroelectronics, Italy. 

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New Publication – NEWCAS23

Improving the key parameters of each analog block is mandatory to push the performance of a data converter to the technology limit. 

Lorenzo Scaletti has presented our last work “A Novel Push-Pull Input Buffer for Wideband ADCs with improved High-Frequency Linearity” at the 21st IEEE Interregional NEWCAS Conference – An IEEE CAS Society Interregional Flagship Conference, Edinburgh, Scotland.

Congratulations to the ARPLab ADC research Team for this new publication.

This work was made possible thanks to the collaboration of Politecnico di Milano with Infineon Technologies, Villach.

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