Tag Archives: PAPER
New Publication – JSSC
We are excited to share that our paper is now accessible in early access in the IEEE Journal of Solid-State Circuits (JSSC)! The article, titled “A Low-Noise Digital PLL with an Adaptive Common-Mode Resonance Tuning Technique for Voltage-Biased Oscillators”, presents an … Continue reading
New Publication – PRIME25
We are pleased to announce that our PhD student, Enrico Albezzano, presented the paper titled “Efficiency Comparison of FVF-Based LDO Voltage Regulators for Ultra-Fast Response Time” at the 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME) held in Taormina, … Continue reading
New Publication – TCAS II
Ever wondered how switch thermal noise affects SAR ADC performance? Our latest paper, “An Analysis of Switch Thermal Noise in SAR Converters,” just published in IEEE Transactions on Circuits and Systems II, explores its impact and shares practical design insights.Congratulations … Continue reading
New Publication – JSSC
In high-performance fractional-N frequency synthesizers, fractional spurs are a critical bottleneck—especially at near-integer channels—degrading both jitter and spectral purity. With next-generation wireless transceivers targeting extremely low jitter (below 80fs), effective spur mitigation becomes essential, often requiring suppression below –60 dBc. In … Continue reading
New Publications – VLSI25
We are pleased to share that two of our PhD students presented their research at the VLSI Symposium 2025 in Kyoto. Michele Rossoni presented “A Fractional-N Digital-PLL based on a Power-Gated Ring-Oscillator and a Frequency-Stabilizing Loop Achieving 74fs Jitter Under … Continue reading
New Publication – CICC25
We’re excited to share that Gabriele Zanoletti represented our team at CICC 2025 in Boston, presenting the paper “A 20MHz-BW 12.3-ENOB NS SAR ADC with a 3rd-order Multi-Input Filter and a PVT-Robust Ratio-Based FIA“. This work is the result of the … Continue reading
New Publications – ISSCC25
The 2025 ISSCC is just around the corner, and we can’t wait to be there!This year, two works from our laboratory have been accepted for presentation at the conference. Simone Mattia Dartizio will present “A 380μW and -242.8dB FoM Digital-PLL-Based … Continue reading
New Publication – JSSC
Low jitter frequency synthesizers are required to achieve high data-rates in modern wireless and wireline transceivers. When battery powered devices utilize these synthesizers their power consumption must be limited, leading to complex design challenges. In our latest article we unveil … Continue reading
New Publication – JSSC
We are thrilled to share our latest work on TI ADCs. This design demonstrates that high-speed TI ADC design requires focus on auxiliary circuits and the sub-ADC to reduce the degradation of single-channel performance in interleaved mode. Our paper proposes … Continue reading
New Publication – JSSC
We are excited to share a deep dive into our latest work on a 10-GHz chirp generator for FMCW radars, based on a digital PLL (DPLL) featuring two-point injection of the modulation signal. In this work, we introduce a novel … Continue reading
