We’re delighted to announce our involvement in the recent CICC event held in Denver. Our research team showcased two significant contributions:
Pietro Salvi presented the work “A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC”
Michele Rossoni introduced “A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector”
Congratulations to the ARPLab PLL research Team for these remarkable accomplishments
