In the upcoming 71st IEEE International Solid-State Circuits Conference (ISSCC) scheduled for February, our laboratory is pleased to announce its participation with three contributions:
In Session number 10 (Frequency Synthesis):
Michele Rossoni will be presenting the paper “An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fs rms Integrated Jitter and -252.4dB FoM”.
Francesco Tesolin will be presenting the paper “A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion”.
In the framework of the Student-Research Preview, Pietro Salvi will be presenting the poster “A 66.7fs-Integrated-Jitter Bang-Bang Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC”.
Congratulations to the ARPLab PLL research Team for these achievements, made also possibile thanks to the contribution of Infineon Technologies, Villach
Hope to see you in San Francisco!
https://www.isscc.org/program-overview
