We are proud to share that ARPLab PhD student Daniele Lodi Rizzini will present our most-recent work on ultra-low jitter fractional-N PLLs, at the IEEE Radio Frequency Integrated Circuit Symposium (RFIC) 2026, in Boston.
The paper, titled “A 25.4fs Jitter Fractional-N Digital PLL with an LC-Based Power-Gated Oscillator and Series-Resonance DCO” will be presented in session Tu2B, on June 9th.
Additionally, for the second year in a row, our work has been selected as one of the finalists for the RFIC Best Student Paper Award!
We look forward to meeting colleagues and RFIC experts at the paper presentation!
