We are delighted to share that PhD student Alessia Ceroni presented the paper “A 12-bit 2-GS/s TI Pipe-SAR ADC with Optimized Signal Distribution and Fully On-Chip Calibrations” at ESSERC 2026, held in Palma, Spain. The paper shows how a carefully designed signal distribution and fully on-chip calibrations let a time-interleaved ADC retain the linearity of its single-core slices, reaching 61.6 dB SNDR and 79.2 dB SFDR near Nyquist at 2 GS/s in 28-nm CMOS. Our warmest congratulations to all the authors!
