Thesis Opportunities

Join our research group!

Here the list of available thesis topics during the A.A. 2023/2024

Further thesis topics will be published soon…

Thesis topics with the [#] flag are not more available

ADC research group:

Baseband ADC system design

  1. Exploration and system-level design of new hybrid ADC architectures for high-speed wireless
  2. Digital equalisation of the frequency response in a multi-channel ADC
  3. Low-power digital algorithms for ADC calibration and non-ideality correction
  4. Design of a Software Defined Radio (SDR) receiver based on a custom prototype ADC

ADC circuit design

  1. Circuit design of a flash-type ADC with low power consumption and compact area
  2. Circuit design of DAC with high linearity and low power consumption
  3. Circuit design of a ring-type amplifier (Ring-Amp) [#]
  4. Design of Fully/partial synthesizable of a fast synchronous/asynchronous SAR logic
  5. Circuit design of a bandgap reference in a 28-nm CMOS process
  6. Circuit design of a Gbit/s data interface
  7. Design of on-chip low-jitter frequency synthesizer for high-speed ADCs.

More topics related to mixed-signal system and circuit design are also available upon request

RF research group:

Transceiver/Frequency Synthesizer system design, RF & mmW circuit design

  1. Validation of a novel measurement method to obtain high resolution characteristics of digital-to-time converters and voltage-controlled oscillators. [NEW]
  2. Fast frequency settling and convergence time techniques to minimize energy loss in Bluetooth Low Energy wake up transceivers. [NEW]
  3. System level architecture analysis for CMOS ultra-low-jitter phase locked loop for next 6G wireless backhaul applications. [NEW]
  4. Design of RF/Mixed-Signal building blocks for CMOS ultra-low-jitter phase locked loop for next 6G wireless backhaul applications. [NEW]
  5. Implementation and measurement validation of real-time digital signal processing automotive FMCW radars systems. [NEW]
  6. Design of a crystal oscillator using energy-efficient techniques to maximize battery life in modern IoT radios. [NEW]
  7. Design of high linearity and high efficiency Wi-Fi 7 digital power-amplifier in CMOS scaled node. [NEW]
  8. Analysis of a digital phase locked loop architecture based on a novel phase detector topology for WLAN applications. [NEW]

PWR research group:

  1. Design of a 700W, 48V-to-3.4V resonant DC-DC converter for data-centers application. [NEW]
  2. Analysis and design of a phase shift control loop for quasi-resonant operation of a resonant DCDC converters.
  3. Design of the power stage and driving network for an integrated 20MHz switching frequency 3-level hybrid buck converter. [NEW]
  4. Design of a novel control network with flying capacitor voltage regulation for an integrated 20MHz switching frequency 3-level hybrid buck converter. [NEW]
  5. VCO control for variable frequency operation in an integrated buck converter with peak-current control (Thesis in collaboration with STMicroelectronics) [NEW]