We are proud to announce that today, June 20 at 4:15 pm (HST), Riccardo Moleri will be presenting our research work titled “A 79.3fs Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique” at the 2024 VLSI Symposium on Technology and Circuits in Honolulu, Hawaii.
Thanks to the entire ARPLab PLL team and Infineon Technologies, Villach, for making it possible!
We look forward to meeting you all in the Honolulu 2 conference room!
