Tag Archives: POLIMI

New Publication – JSSC

Posted on October 31, 2024 by admin

Low jitter frequency synthesizers are required to achieve high data-rates in modern wireless and wireline transceivers. When battery powered devices utilize these synthesizers their power consumption must be limited, leading to complex design challenges. In our latest article we unveil … Continue reading →

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New Publication – JSSC

Posted on October 24, 2024 by admin

We are thrilled to share our latest work on TI ADCs. This design demonstrates that high-speed TI ADC design requires focus on auxiliary circuits and the sub-ADC to reduce the degradation of single-channel performance in interleaved mode. Our paper proposes … Continue reading →

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New Publication – JSSC

Posted on October 15, 2024 by admin

We are excited to share a deep dive into our latest work on a 10-GHz chirp generator for FMCW radars, based on a digital PLL (DPLL) featuring two-point injection of the modulation signal. In this work, we introduce a novel … Continue reading →

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New Publication – PRIME24

Posted on August 14, 2024 by admin

Alessia Ceroni presented our recent work titled ‘A highly energy-efficient FIA-based AZ-free Ring Amplifier for Pipeline SAR ADC’ at the 19th International Conference On PhD Research in Microelectronics and Electronics (PRIME) in Larnaka, Cyprus.  Congratulations to the ARPLab ADC research … Continue reading →

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New Publication – VLSI24

Posted on June 20, 2024 by admin

We are proud to announce that today, June 20 at 4:15 pm (HST), Riccardo Moleri will be presenting our research work titled “A 79.3fs Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique” at the 2024 VLSI Symposium on … Continue reading →

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New Publications – CICC24

Posted on May 13, 2024 by admin

We’re delighted to announce our involvement in the recent CICC event held in Denver. Our research team showcased two significant contributions: Pietro Salvi presented the work “A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC” Michele Rossoni introduced “A … Continue reading →

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New Publications – APEC24

Posted on March 7, 2024 by admin

Our team has just wrapped up an insightful journey at the Applied Power Electronics Conference (APEC 2024), showcasing three papers. APEC stands as the premier conference in the realm of medium-low power conversion applications (<1kW). Huge congratulations to Paolo Melillo … Continue reading →

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New Award – ISSCC 2023

Posted on February 21, 2024 by admin

ARPLab has just received the ISSCC 2023 Jan Van Vessem Award for Oustanding European Paper for the paper “A 76.7fs-Integrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.” The paper introduced a … Continue reading →

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New Publications – ISSCC24

Posted on January 30, 2024 by admin

In the upcoming 71st IEEE International Solid-State Circuits Conference (ISSCC) scheduled for February, our laboratory is pleased to announce its participation with three contributions: In Session number 10 (Frequency Synthesis): Michele Rossoni will be presenting the paper “An 8.75GHz Fractional-N … Continue reading →

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Circuit Technology Symposium at The Seoul National University

Posted on December 30, 2023 by admin

Earlier this month, our PhD candidate Michele Rossoni visited Seoul National University, where he met with students from Professor Jaehyouk Choi’s research laboratory on RF electronics. It was a pleasure to meet other researchers working in our same field, share … Continue reading →

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