Tag Archives: POLIMI

New Publication – JSSC

In high-performance fractional-N frequency synthesizers, fractional spurs are a critical bottleneck—especially at near-integer channels—degrading both jitter and spectral purity. With next-generation wireless transceivers targeting extremely low jitter (below 80fs), effective spur mitigation becomes essential, often requiring suppression below –60 dBc. In … Continue reading

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New Publications – VLSI25

We are pleased to share that two of our PhD students presented their research at the VLSI Symposium 2025 in Kyoto. Michele Rossoni presented “A Fractional-N Digital-PLL based on a Power-Gated Ring-Oscillator and a Frequency-Stabilizing Loop Achieving 74fs Jitter Under … Continue reading

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New Publication – CICC25

We’re excited to share that Gabriele Zanoletti represented our team at CICC 2025 in Boston, presenting the paper “A 20MHz-BW 12.3-ENOB NS SAR ADC with a 3rd-order Multi-Input Filter and a PVT-Robust Ratio-Based FIA“. This work is the result of the … Continue reading

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Staff – Celebrations

Luca Ricci, Paolo Melillo and Gabriele Bè successfully defended their doctoral thesis on March 6th. Congratulations on this important achievement! We would like to wish you good luck in your future career and thank you for your hard work and … Continue reading

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New Publications – ISSCC25

The 2025 ISSCC is just around the corner, and we can’t wait to be there!This year, two works from our laboratory have been accepted for presentation at the conference. Simone Mattia Dartizio will present “A 380μW and -242.8dB FoM Digital-PLL-Based … Continue reading

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New Publication – JSSC

Low jitter frequency synthesizers are required to achieve high data-rates in modern wireless and wireline transceivers. When battery powered devices utilize these synthesizers their power consumption must be limited, leading to complex design challenges. In our latest article we unveil … Continue reading

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New Publication – JSSC

We are thrilled to share our latest work on TI ADCs. This design demonstrates that high-speed TI ADC design requires focus on auxiliary circuits and the sub-ADC to reduce the degradation of single-channel performance in interleaved mode. Our paper proposes … Continue reading

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New Publication – JSSC

We are excited to share a deep dive into our latest work on a 10-GHz chirp generator for FMCW radars, based on a digital PLL (DPLL) featuring two-point injection of the modulation signal. In this work, we introduce a novel … Continue reading

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New Publication – PRIME24

Alessia Ceroni presented our recent work titled ‘A highly energy-efficient FIA-based AZ-free Ring Amplifier for Pipeline SAR ADC’ at the 19th International Conference On PhD Research in Microelectronics and Electronics (PRIME) in Larnaka, Cyprus.  Congratulations to the ARPLab ADC research … Continue reading

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New Publication – VLSI24

We are proud to announce that today, June 20 at 4:15 pm (HST), Riccardo Moleri will be presenting our research work titled “A 79.3fs Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique” at the 2024 VLSI Symposium on … Continue reading

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