ARPLab

We’re delighted to announce our involvement in the recent CICC event held in Denver. Our research team showcased two significant contributions:

Pietro Salvi presented the work “A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC”

Michele Rossoni introduced “A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector”

Congratulations to the ARPLab PLL research Team for these remarkable accomplishments

ARPLab has just received the ISSCC 2023 Jan Van Vessem Award for Oustanding European Paper for the paper “A 76.7fs-Integrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.”

The paper introduced a new concept to design linear digital-to-time converters, the “Inverse-Constant-Slope DTC”, that is crucial for achieving beyond state-of-the-art performance in frequency synthesizers. The PLL prototype was developed in the ARPLab laboratory at the Department of Electronics, Information and Bioengineering, Politecnico di Milano and manufactured using a 28nm CMOS TSMC technology. The results concretely demonstrate the feasibility of bang-bang PLLs for high-performance wireless applications.