We are delighted to share that PhD student Alessia Ceroni presented the paper “A 12-bit 2-GS/s TI Pipe-SAR ADC with Optimized Signal Distribution and Fully On-Chip Calibrations” at ESSERC 2026, held in Palma, Spain. The paper shows how a carefully designed signal distribution and fully on-chip calibrations let a time-interleaved ADC retain the linearity of its single-core slices, reaching 61.6 dB SNDR and 79.2 dB SFDR near Nyquist at 2 GS/s in 28-nm CMOS. Our warmest congratulations to all the authors!
We are proud to share that ARPLab PhD student Daniele Lodi Rizzini will present our most-recent work on ultra-low jitter fractional-N PLLs, at the IEEE Radio Frequency Integrated Circuit Symposium (RFIC) 2026, in Boston.
The paper, titled “A 25.4fs Jitter Fractional-N Digital PLL with an LC-Based Power-Gated Oscillator and Series-Resonance DCO” will be presented in session Tu2B, on June 9th.
Additionally, for the second year in a row, our work has been selected as one of the finalists for the RFIC Best Student Paper Award!
We look forward to meeting colleagues and RFIC experts at the paper presentation!
We are very proud to announce that, for the first time, three works from our laboratory ARPLab – DEIB, Politecnico di Milano, have been accepted for presentation at the International Solid-State Circuits Conference (ISSCC) 2026.
If you are planning to attend ISSCC in San Francisco next week, don’t miss the following presentations from our PhD candidates:
Tuesday, February 17th– Session 11: “Pipeline and Ultra-High-Speed Data Converters” Michele Rocco will present: “A 500MS/s 12b Pipe-SAR ADC Using a Triple-Cascode FIA with Virtual Supply Extension.”
Tuesday, February 17th– Session 12: “Frequency Synthesizers and VCOs” Damiano Fagotti will present: “A Fractional-N Digital PLL with a Supply-Insensitive DTC Achieving –62dBc Spur and 69fs Jitter Under 10mVpp Sinusoidal DTC Supply Ripple and 6.2mVrms DTC Supply Noise.”
Pietro Salvi will present: “A –66dBc Worst-Fractional-Spur and 58fs-Jitter Fractional-N Digital PLL Using a Supply-Resilient Pseudo-Differential Inverse-Constant-Slope DTC.”
We are excited to share that our paper is now accessible in early access in the IEEE Journal of Solid-State Circuits (JSSC)!
The article, titled “A Low-Noise Digital PLL with an Adaptive Common-Mode Resonance Tuning Technique for Voltage-Biased Oscillators”, presents an in-depth analysis and extended results of the work we previously presented at the 2025 IEEE International Solid-State Circuits Conference (ISSCC).
This work introduces a new background calibration technique for voltage-biased oscillators, capable of optimizing their phase-noise performance across the entire tuning range by adaptively adjusting the ratio between common-mode and differential-mode capacitance.
The test chip, fabricated in a 28-nm CMOS process, achieves 45.8-fs integrated jitter and −146.6-dBc/Hz phase noise at 10-MHz offset from a 4.75-GHz carrier.
If you are interested in digital PLLs and digitally controlled oscillator design, you can find the article here: [URL]
We are pleased to announce that our PhD student, Enrico Albezzano, presented the paper titled “Efficiency Comparison of FVF-Based LDO Voltage Regulators for Ultra-Fast Response Time” at the 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME) held in Taormina, Italy. This work demonstrates the benefits of advanced stabilization techniques in fully integrated linear regulators. Congratulations to everyone involved!
Ever wondered how switch thermal noise affects SAR ADC performance? Our latest paper, “An Analysis of Switch Thermal Noise in SAR Converters,” just published in IEEE Transactions on Circuits and Systems II, explores its impact and shares practical design insights. Congratulations to our PhD candidates Ilaria Ferrari, Gabriele Zanoletti and all the authors!
Giacomo Tombolan presented “Power-Reduction Technique for Time-to-Digital Converters in 28-nm CMOS Process” — and achieved 2nd place for Best Paper Award!
A huge thank you to everyone who made the event memorable. We’re proud to have contributed to a vibrant environment for technical exchange, innovation, and collaboration across academia and industry.
Excited to share that our article “A Low-Noise Fractional-N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC” is now published in the prestigious IEEE Journal of Solid-State Circuits (Vol. 60, Issue 7)!
This work presents design guidelines and a rigorous theoretical analysis of inverse-constant-slope DTC architectures—demonstrating their potential for achieving <67fs integrated jitter and <−63dBc fractional spurs at 9.25GHz with a 125MHz reference.
If you’re working on frequency synthesizers for wireless or wireline systems and aiming for low jitter and high spectral purity, we invite you to check it out!
In high-performance fractional-N frequency synthesizers, fractional spurs are a critical bottleneck—especially at near-integer channels—degrading both jitter and spectral purity. With next-generation wireless transceivers targeting extremely low jitter (below 80fs), effective spur mitigation becomes essential, often requiring suppression below –60 dBc.
In our latest work, we present the design of a 10GHz digital fractional-N PLL that achieves sub-80fs rms jitter with in-band fractional spurs below -60dBc at near-integer channels.
The key enabler is a novel phase detection architecture with multiple parallel paths, comprising each a digital-to-time converter and a phase-detector, allowing fractional spur cancellation without increasing PLL in-band noise.
If you’re working on low-jitter clocking or next-gen transceivers, we invite you to check it out!
We are pleased to share that two of our PhD students presented their research at the VLSI Symposium 2025 in Kyoto.
Michele Rossoni presented “A Fractional-N Digital-PLL based on a Power-Gated Ring-Oscillator and a Frequency-Stabilizing Loop Achieving 74fs Jitter Under 3mVpp Supply Ripple”
Damiano Fagotti presented “A 58.9fs-Jitter Fractional-N Digital PLL Using a Double-Edge Variable-Slope DTC”
Congratulations to the ARPLab RF team for this achievement, and sincere thanks to the VLSI Symposium Secretariat for organizing an outstanding conference.
