Excited to share that our article “A Low-Noise Fractional-N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC” is now published in the prestigious IEEE Journal of Solid-State Circuits (Vol. 60, Issue 7)!
This work presents design guidelines and a rigorous theoretical analysis of inverse-constant-slope DTC architectures—demonstrating their potential for achieving <67fs integrated jitter and <−63dBc fractional spurs at 9.25GHz with a 125MHz reference.
If you’re working on frequency synthesizers for wireless or wireline systems and aiming for low jitter and high spectral purity, we invite you to check it out!
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