Ever wondered how switch thermal noise affects SAR ADC performance? Our latest paper, “An Analysis of Switch Thermal Noise in SAR Converters,” just published in IEEE Transactions on Circuits and Systems II, explores its impact and shares practical design insights.
Congratulations to our PhD candidates Ilaria Ferrari, Gabriele Zanoletti and all the authors!
Read the full paper on IEEE Xplore: https://ieeexplore.ieee.org/document/11205474
We’re excited to share that our team recently took part in the 22nd International Conference on IC Design and Technology (ICICDT) in Lecce, Italy!
Alessia Ceroni presented her research on
“A Complementary Bootstrapped Sampler for High-Frequency High-Resolution ADCs”
Mauro Leoncini presented
“A Monolithic Quasi-Resonant Switched-Capacitor Converter with Dual-Loop Time-Based Controller”
Giacomo Tombolan presented
“Power-Reduction Technique for Time-to-Digital Converters in 28-nm CMOS Process”
— and achieved 2nd place for Best Paper Award!
A huge thank you to everyone who made the event memorable. We’re proud to have contributed to a vibrant environment for technical exchange, innovation, and collaboration across academia and industry.
Excited to share that our article “A Low-Noise Fractional-N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC” is now published in the prestigious IEEE Journal of Solid-State Circuits (Vol. 60, Issue 7)!
This work presents design guidelines and a rigorous theoretical analysis of inverse-constant-slope DTC architectures—demonstrating their potential for achieving <67fs integrated jitter and <−63dBc fractional spurs at 9.25GHz with a 125MHz reference.
If you’re working on frequency synthesizers for wireless or wireline systems and aiming for low jitter and high spectral purity, we invite you to check it out!
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In high-performance fractional-N frequency synthesizers, fractional spurs are a critical bottleneck—especially at near-integer channels—degrading both jitter and spectral purity. With next-generation wireless transceivers targeting extremely low jitter (below 80fs), effective spur mitigation becomes essential, often requiring suppression below –60 dBc.
In our latest work, we present the design of a 10GHz digital fractional-N PLL that achieves sub-80fs rms jitter with in-band fractional spurs below -60dBc at near-integer channels.
The key enabler is a novel phase detection architecture with multiple parallel paths, comprising each a digital-to-time converter and a phase-detector, allowing fractional spur cancellation without increasing PLL in-band noise.
If you’re working on low-jitter clocking or next-gen transceivers, we invite you to check it out!
We are pleased to share that two of our PhD students presented their research at the VLSI Symposium 2025 in Kyoto.
Michele Rossoni presented “A Fractional-N Digital-PLL based on a Power-Gated Ring-Oscillator and a Frequency-Stabilizing Loop Achieving 74fs Jitter Under 3mVpp Supply Ripple”
Damiano Fagotti presented “A 58.9fs-Jitter Fractional-N Digital PLL Using a Double-Edge Variable-Slope DTC”
Congratulations to the ARPLab RF team for this achievement, and sincere thanks to the VLSI Symposium Secretariat for organizing an outstanding conference.
We’re excited to share that Gabriele Zanoletti represented our team at CICC 2025 in Boston, presenting the paper “A 20MHz-BW 12.3-ENOB NS SAR ADC with a 3rd-order Multi-Input Filter and a PVT-Robust Ratio-Based FIA“.
This work is the result of the ADC team’s first research project focused on noise-shaping ADC architectures, and we’re proud to have had the opportunity to present our findings on an international stage.
This achievement was made possible thanks to the collaboration of Politecnico di Milano with Infineon Technologies, Villach.
Luca Ricci, Paolo Melillo and Gabriele Bè successfully defended their doctoral thesis on March 6th. Congratulations on this important achievement! We would like to wish you good luck in your future career and thank you for your hard work and contribution to the lab!
The 2025 ISSCC is just around the corner, and we can’t wait to be there!
This year, two works from our laboratory have been accepted for presentation at the conference.
Simone Mattia Dartizio will present “A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS,” and Stefano Gallucci will present “A 4.75GHz Digital PLL with 45.8fs Integrated Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning.”
Both presentations will take place in Session 34: “Digital PLLs and Waveform-Shaping VCOs.”
We look forward to meeting you there.
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Low jitter frequency synthesizers are required to achieve high data-rates in modern wireless and wireline transceivers. When battery powered devices utilize these synthesizers their power consumption must be limited, leading to complex design challenges.
In our latest article we unveil the design of a fractional-N digital PLL that achieves sub-60fs rms jitter while dissipating only 17.5mW, leading to best-in-class power efficiency among ultra-low-jitter fractional-N PLLs.
These performance have been obtained by adopting a novel digital-to-time converter architecture, capable to provide an highly linear controllable delay with both low noise and low power consumption.
If you are interested in the topic please consider checking it out.
We are thrilled to share our latest work on TI ADCs.
This design demonstrates that high-speed TI ADC design requires focus on auxiliary circuits and the sub-ADC to reduce the degradation of single-channel performance in interleaved mode.
Our paper proposes a 2-GSps TI ADC implemented in a 28-nm bulk CMOS process. The ADC interleaves eight 11-bit 250 MS/s SAR ADCs. It achieves a 9.2-ENOB and a 70.1-dB SFDR close to the Nyquist frequency. On a 1-GHz bandwidth, the TI ADC SNDR degrades only by 1.76 dB compared to the sub-ADC performance.
You might find the paper interesting if you’re working on TI ADC! Check out the article on early access in the IEEE Journal of Solid-State Circuits for all the details.
This work was made possible thanks to the collaboration of Politecnico di Milano with Infineon Technologies, Villach.
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