ARPLab

We are pleased to share that two of our PhD students presented their research at the VLSI Symposium 2025 in Kyoto.

Michele Rossoni presented “A Fractional-N Digital-PLL based on a Power-Gated Ring-Oscillator and a Frequency-Stabilizing Loop Achieving 74fs Jitter Under 3mVpp Supply Ripple”

Damiano Fagotti presented “A 58.9fs-Jitter Fractional-N Digital PLL Using a Double-Edge Variable-Slope DTC”

Congratulations to the ARPLab RF team for this achievement, and sincere thanks to the VLSI Symposium Secretariat for organizing an outstanding conference.

Low jitter frequency synthesizers are required to achieve high data-rates in modern wireless and wireline transceivers. When battery powered devices utilize these synthesizers their power consumption must be limited, leading to complex design challenges.

In our latest article we unveil the design of a fractional-N digital PLL that achieves sub-60fs rms jitter while dissipating only 17.5mW, leading to best-in-class power efficiency among ultra-low-jitter fractional-N PLLs.

These performance have been obtained by adopting a novel digital-to-time converter architecture, capable to provide an highly linear controllable delay with both low noise and low power consumption.

If you are interested in the topic please consider checking it out.

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