ARPLab

In high-performance fractional-N frequency synthesizers, fractional spurs are a critical bottleneck—especially at near-integer channels—degrading both jitter and spectral purity. With next-generation wireless transceivers targeting extremely low jitter (below 80fs), effective spur mitigation becomes essential, often requiring suppression below –60 dBc.

In our latest work, we present the design of a 10GHz digital fractional-N PLL that achieves sub-80fs rms jitter with in-band fractional spurs below -60dBc at near-integer channels.

The key enabler is a novel phase detection architecture with multiple parallel paths, comprising each a digital-to-time converter and a phase-detector, allowing fractional spur cancellation without increasing PLL in-band noise.

If you’re working on low-jitter clocking or next-gen transceivers, we invite you to check it out!

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We are pleased to share that two of our PhD students presented their research at the VLSI Symposium 2025 in Kyoto.

Michele Rossoni presented “A Fractional-N Digital-PLL based on a Power-Gated Ring-Oscillator and a Frequency-Stabilizing Loop Achieving 74fs Jitter Under 3mVpp Supply Ripple”

Damiano Fagotti presented “A 58.9fs-Jitter Fractional-N Digital PLL Using a Double-Edge Variable-Slope DTC”

Congratulations to the ARPLab RF team for this achievement, and sincere thanks to the VLSI Symposium Secretariat for organizing an outstanding conference.

Low jitter frequency synthesizers are required to achieve high data-rates in modern wireless and wireline transceivers. When battery powered devices utilize these synthesizers their power consumption must be limited, leading to complex design challenges.

In our latest article we unveil the design of a fractional-N digital PLL that achieves sub-60fs rms jitter while dissipating only 17.5mW, leading to best-in-class power efficiency among ultra-low-jitter fractional-N PLLs.

These performance have been obtained by adopting a novel digital-to-time converter architecture, capable to provide an highly linear controllable delay with both low noise and low power consumption.

If you are interested in the topic please consider checking it out.

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