One month to the 70th IEEE International Solid-State Circuits Conference (ISSCC) that will be held in San Francisco, CA and we can’t wait to be there!
This year two papers from our laboratory were be accepted for presentation:
Simone Dartizio will be presenting the paper “A 76.7fs-Integrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering”.
Giacomo Castoro will be presenting the paper “A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology”.
Congratulations to the ARPLab PLL research Team for the achievement.
These works were made possible thanks to the collaboration of Politecnico di Milano with Infineon Technologies, Villach.
https://www.isscc.org/conference-timetable
