We are proud to announce that our phd candidate Luca Ricci has presented our last work: “A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS” at the 2023 Symposium on VLSI Technology and Circuits, Kyoto, Japan.
Congratulations to the ARPLab ADC research Team for the achievement.
This work was made possible thanks to the collaboration of Politecnico di Milano with Infineon Technologies, Villach.
One month to the 70th IEEE International Solid-State Circuits Conference (ISSCC) that will be held in San Francisco, CA and we can’t wait to be there!
This year two papers from our laboratory were be accepted for presentation:
Simone Dartizio will be presenting the paper “A 76.7fs-Integrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering”.
Giacomo Castoro will be presenting the paper “A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology”.
Congratulations to the ARPLab PLL research Team for the achievement.
These works were made possible thanks to the collaboration of Politecnico di Milano with Infineon Technologies, Villach.
https://www.isscc.org/conference-timetable
Alessandro Dago will be presenting the paper “High Power Density 4:1 Resonant Switched-Capacitor DC-DC Converter for Pol Applications”, in the T17 – Hybrid/Switched Capacitor Converters session at the next APEC 2023,Orlando, FL, USA. Congratulations on your achievement! [URL]
Professor Levantino was a keynote speaker at the 30th IFIP/IEEE VLSI -SoC conference (URL) held in Patras, Greece, delivering a speech on “Designing Phase-Locked Loops in Modern CMOS Technologies”
Mauro Leoncini, Alessandro Dago and Paolo Melillo presented their three papers at the 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), held in Villasimius, Sardinia, Italy in June 2022. Mauro Leoncini was also the recipient of the gold leaf award, the certificate reserved only for the top 10% papers.
Congratulations to the ARPLab Power research Team for all these achievements. This work was possible thanks to the collaboration of Politecnico di Milano with STMicroelectronics, Italy.
Gabriele Be’ will be presenting the paper “A 900-MS/S SAR-Based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations”, at the IEEE MWSCAS 2022. The extended version of this paper was also published in the journal Transactions on Circuits and Systems II . This work was possible thanks to the collaboration of Politecnico di Milano with Infineon Technologies, Villach. [TCAS] [MWSCAS]
Luca Ricci will be presenting the paper “Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs”, at the next IEEE ISCAS 2022. [URL]
Lorenzo Scaletti will be presenting the paper “A 10.2-ENOB, 150-MS/s Redundant SAR ADC with a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters”, at the next IEEE NEWCAS 2022. [URL]
Francesco Buccoleri will be presenting the paper “A 9GHz 72fs-Total-Integrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler”, at the next IEEE Custom Integrated Circuits Conference (CICC). This work was possible thanks to the collaboration of Politecnico di Milano with Infineon Technologies, Villach and University of Padova. [URL]
Simone Dartizio will be presenting the paper “A 68.6-fs-rms-Total-Integrated-Jitter and 1.56-us-Locking-Time Fractional-N Bang-Bang PLL Based on a Type-II Gear Shifting and Adaptive Frequency Switching” at the next IEEE International Solid-State Circuits Conference (ISSCC). This work was possible thanks to the collaboration of Politecnico di Milano with Infineon Technologies, Villach and University of Padova. [URL]
