Monthly Archives: October 2024
New Publication – JSSC
Low jitter frequency synthesizers are required to achieve high data-rates in modern wireless and wireline transceivers. When battery powered devices utilize these synthesizers their power consumption must be limited, leading to complex design challenges. In our latest article we unveil … Continue reading
New Publication – JSSC
We are thrilled to share our latest work on TI ADCs. This design demonstrates that high-speed TI ADC design requires focus on auxiliary circuits and the sub-ADC to reduce the degradation of single-channel performance in interleaved mode. Our paper proposes … Continue reading
New Publication – JSSC
We are excited to share a deep dive into our latest work on a 10-GHz chirp generator for FMCW radars, based on a digital PLL (DPLL) featuring two-point injection of the modulation signal. In this work, we introduce a novel … Continue reading
