Luca Ricci, Paolo Melillo and Gabriele Bè successfully defended their doctoral thesis on March 6th. Congratulations on this important achievement! We would like to wish you good luck in your future career and thank you for your hard work and contribution to the lab!
The 2025 ISSCC is just around the corner, and we can’t wait to be there!
This year, two works from our laboratory have been accepted for presentation at the conference.
Simone Mattia Dartizio will present “A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS,” and Stefano Gallucci will present “A 4.75GHz Digital PLL with 45.8fs Integrated Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning.”
Both presentations will take place in Session 34: “Digital PLLs and Waveform-Shaping VCOs.”
We look forward to meeting you there.
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Low jitter frequency synthesizers are required to achieve high data-rates in modern wireless and wireline transceivers. When battery powered devices utilize these synthesizers their power consumption must be limited, leading to complex design challenges.
In our latest article we unveil the design of a fractional-N digital PLL that achieves sub-60fs rms jitter while dissipating only 17.5mW, leading to best-in-class power efficiency among ultra-low-jitter fractional-N PLLs.
These performance have been obtained by adopting a novel digital-to-time converter architecture, capable to provide an highly linear controllable delay with both low noise and low power consumption.
If you are interested in the topic please consider checking it out.
We are thrilled to share our latest work on TI ADCs.
This design demonstrates that high-speed TI ADC design requires focus on auxiliary circuits and the sub-ADC to reduce the degradation of single-channel performance in interleaved mode.
Our paper proposes a 2-GSps TI ADC implemented in a 28-nm bulk CMOS process. The ADC interleaves eight 11-bit 250 MS/s SAR ADCs. It achieves a 9.2-ENOB and a 70.1-dB SFDR close to the Nyquist frequency. On a 1-GHz bandwidth, the TI ADC SNDR degrades only by 1.76 dB compared to the sub-ADC performance.
You might find the paper interesting if you’re working on TI ADC! Check out the article on early access in the IEEE Journal of Solid-State Circuits for all the details.
This work was made possible thanks to the collaboration of Politecnico di Milano with Infineon Technologies, Villach.
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We are excited to share a deep dive into our latest work on a 10-GHz chirp generator for FMCW radars, based on a digital PLL (DPLL) featuring two-point injection of the modulation signal.
In this work, we introduce a novel digital predistortion (DPD) algorithm that addresses the challenges posed by the nonlinear and non-smooth tuning curve of a digitally controlled oscillator (DCO) optimized for low phase noise.
If you’re working in radar technology or digital PLL design, you might find this especially interesting! Check out the article for all the details [URL]
Alessia Ceroni presented our recent work titled ‘A highly energy-efficient FIA-based AZ-free Ring Amplifier for Pipeline SAR ADC’ at the 19th International Conference On PhD Research in Microelectronics and Electronics (PRIME) in Larnaka, Cyprus.
Congratulations to the ARPLab ADC research Team for their latest publication.
We are proud to announce that today, June 20 at 4:15 pm (HST), Riccardo Moleri will be presenting our research work titled “A 79.3fs Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique” at the 2024 VLSI Symposium on Technology and Circuits in Honolulu, Hawaii.
Thanks to the entire ARPLab PLL team and Infineon Technologies, Villach, for making it possible!
We look forward to meeting you all in the Honolulu 2 conference room!
Alessandro Dago, Francesco Buccoleri e Lorenzo Scaletti have moved respectively to Allegro Microsystems (Assago, Italy), Kandou (Lausanne, Switzerland) and Infienon Technologies (Villach, Austria). Good luck Alessandro, Francesco e Lorenzo and thank you for your hard work and contribution to the lab!
We’re delighted to announce our involvement in the recent CICC event held in Denver. Our research team showcased two significant contributions:
Pietro Salvi presented the work “A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC”
Michele Rossoni introduced “A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector”
Congratulations to the ARPLab PLL research Team for these remarkable accomplishments
Our team has just wrapped up an insightful journey at the Applied Power Electronics Conference (APEC 2024), showcasing three papers. APEC stands as the premier conference in the realm of medium-low power conversion applications (<1kW). Huge congratulations to Paolo Melillo and Simone Zaffin for their outstanding presentations, earning them the best presentation awards in their respective sessions!
