ARPLab

We are excited to share that our paper is now accessible in early access in the IEEE Journal of Solid-State Circuits (JSSC)!

The article, titled “A Low-Noise Digital PLL with an Adaptive Common-Mode Resonance Tuning Technique for Voltage-Biased Oscillators”, presents an in-depth analysis and extended results of the work we previously presented at the 2025 IEEE International Solid-State Circuits Conference (ISSCC).

This work introduces a new background calibration technique for voltage-biased oscillators, capable of optimizing their phase-noise performance across the entire tuning range by adaptively adjusting the ratio between common-mode and differential-mode capacitance.

The test chip, fabricated in a 28-nm CMOS process, achieves 45.8-fs integrated jitter and −146.6-dBc/Hz phase noise at 10-MHz offset from a 4.75-GHz carrier.

If you are interested in digital PLLs and digitally controlled oscillator design, you can find the article here: [URL]

In high-performance fractional-N frequency synthesizers, fractional spurs are a critical bottleneck—especially at near-integer channels—degrading both jitter and spectral purity. With next-generation wireless transceivers targeting extremely low jitter (below 80fs), effective spur mitigation becomes essential, often requiring suppression below –60 dBc.

In our latest work, we present the design of a 10GHz digital fractional-N PLL that achieves sub-80fs rms jitter with in-band fractional spurs below -60dBc at near-integer channels.

The key enabler is a novel phase detection architecture with multiple parallel paths, comprising each a digital-to-time converter and a phase-detector, allowing fractional spur cancellation without increasing PLL in-band noise.

If you’re working on low-jitter clocking or next-gen transceivers, we invite you to check it out!

[URL]

We are pleased to share that two of our PhD students presented their research at the VLSI Symposium 2025 in Kyoto.

Michele Rossoni presented “A Fractional-N Digital-PLL based on a Power-Gated Ring-Oscillator and a Frequency-Stabilizing Loop Achieving 74fs Jitter Under 3mVpp Supply Ripple”

Damiano Fagotti presented “A 58.9fs-Jitter Fractional-N Digital PLL Using a Double-Edge Variable-Slope DTC”

Congratulations to the ARPLab RF team for this achievement, and sincere thanks to the VLSI Symposium Secretariat for organizing an outstanding conference.