We are proud to share that ARPLab PhD student Daniele Lodi Rizzini will present our most-recent work on ultra-low jitter fractional-N PLLs, at the IEEE Radio Frequency Integrated Circuit Symposium (RFIC) 2026, in Boston.<\/p>\n\n\n\n
The paper, titled \u201cA 25.4fs Jitter Fractional-N Digital PLL with an LC-Based Power-Gated Oscillator and Series-Resonance DCO\u201d will be presented in session Tu2B, on June 9th<\/em>.<\/p>\n\n\n\n Additionally, for the second year in a row, our work has been selected as one of the finalists for the RFIC Best Student Paper Award!<\/p>\n\n\n\n We look forward to meeting colleagues and RFIC experts at the paper presentation!<\/p>\n\n\n\n <\/p>\n","protected":false},"excerpt":{"rendered":" We are proud to share that ARPLab PhD student Daniele Lodi Rizzini will present our most-recent work on ultra-low jitter fractional-N PLLs, at the IEEE Radio Frequency Integrated Circuit Symposium (RFIC) 2026, in Boston. The paper, titled \u201cA 25.4fs Jitter Fractional-N Digital PLL with an LC-Based … Continue reading