Excited to share that our article \u201cA Low-Noise Fractional-N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC\u201d is now published in the prestigious IEEE Journal of Solid-State Circuits (Vol. 60, Issue 7)!
This work presents design guidelines and a rigorous theoretical analysis of inverse-constant-slope DTC architectures\u2014demonstrating their potential for achieving <67fs integrated jitter and <\u221263dBc fractional spurs at 9.25GHz with a 125MHz reference.
If you’re working on frequency synthesizers for wireless or wireline systems and aiming for low jitter and high spectral purity, we invite you to check it out!<\/p>\n\n\n\n
[URL<\/a>]<\/p>\n\n\n\n Excited to share that our article \u201cA Low-Noise Fractional-N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC\u201d is now published in the prestigious IEEE Journal of Solid-State Circuits (Vol. 60, Issue 7)! This work presents design guidelines and a rigorous theoretical … Continue reading ![\"\"](\"https:\/\/arplab.deib.polimi.it\/wp-content\/uploads\/2025\/07\/jsscsalvi-1024x690.jpg\")
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