In high-performance fractional-N frequency synthesizers, fractional spurs are a critical bottleneck\u2014especially at near-integer channels\u2014degrading both jitter and spectral purity. With next-generation wireless transceivers targeting extremely low jitter (below 80fs), effective spur mitigation becomes essential, often requiring suppression below \u201360\u202fdBc.<\/p>\n\n\n\n
In our latest work, we present the design of a 10GHz digital fractional-N PLL that achieves sub-80fs rms jitter with in-band fractional spurs below -60dBc at near-integer channels.<\/p>\n\n\n\n
The key enabler is a novel phase detection architecture with multiple parallel paths, comprising each a digital-to-time converter and a phase-detector, allowing fractional spur cancellation without increasing PLL in-band noise.<\/p>\n\n\n\n
If you’re working on low-jitter clocking or next-gen transceivers, we invite you to check it out!<\/p>\n\n\n\n
[URL]<\/a><\/p>\n\n\n\n In high-performance fractional-N frequency synthesizers, fractional spurs are a critical bottleneck\u2014especially at near-integer channels\u2014degrading both jitter and spectral purity. With next-generation wireless transceivers targeting extremely low jitter (below 80fs), effective spur mitigation becomes essential, often requiring suppression below \u201360\u202fdBc. In … Continue reading ![\"\"](\"https:\/\/arplab.deib.polimi.it\/wp-content\/uploads\/2025\/06\/Final_Image_v2.png\")
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