We are thrilled to share our latest work on TI ADCs.<\/p>\n\n\n\n
This design demonstrates that high-speed TI ADC design requires focus on auxiliary circuits and the sub-ADC to reduce the degradation of single-channel performance in interleaved mode.<\/p>\n\n\n\n
Our paper proposes a 2-GSps TI ADC implemented in a 28-nm bulk CMOS process. The ADC interleaves eight 11-bit 250 MS\/s SAR ADCs. It achieves a 9.2-ENOB and a 70.1-dB SFDR close to the Nyquist frequency. On a 1-GHz bandwidth, the TI ADC SNDR degrades only by 1.76 dB compared to the sub-ADC performance. <\/p>\n\n\n\n
You might find the paper interesting if you’re working on TI ADC! Check out the article on early access in the IEEE Journal of Solid-State Circuits for all the details. <\/p>\n\n\n\n
This\u00a0work\u00a0was\u00a0made\u00a0possible thanks to the collaboration of\u00a0Politecnico di Milano\u00a0with\u00a0Infineon Technologies, Villach.<\/p>\n\n\n\n
[URL<\/a>]<\/p>\n\n\n\n <\/p>\n","protected":false},"excerpt":{"rendered":" We are thrilled to share our latest work on TI ADCs. This design demonstrates that high-speed TI ADC design requires focus on auxiliary circuits and the sub-ADC to reduce the degradation of single-channel performance in interleaved mode. Our paper proposes … Continue reading ![\"\"](\"https:\/\/arplab.deib.polimi.it\/wp-content\/uploads\/2024\/10\/tiadc.jpg\")
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