![\"\"](\"https:\/\/arplab.deib.polimi.it\/wp-content\/uploads\/2023\/05\/adc2-1024x1024.jpg\")
<\/figure>
2-GS\/s TI-ADC for 5G baseband (2022)<\/strong><\/h3>\n\n\n\n2-GS\/s Time-Interleaved ADC in TSMC 28nm CMOS based on SAR ADC with on-chip digital calibration.<\/p>\n<\/div><\/div>\n\n\n\n
\n
Dual Mode buck converter (2022)<\/strong><\/h3>\n\n\n\nDual Mode buck converter with constant bandwidth time-based control and 20uA quiescent current for industrial applications.<\/p>\n<\/div>![\"\"](\"https:\/\/arplab.deib.polimi.it\/wp-content\/uploads\/2023\/05\/CHIPRisorsa-12-810x1024.png\")
<\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
![\"\"](\"https:\/\/arplab.deib.polimi.it\/wp-content\/uploads\/2022\/02\/Screenshot-2021-10-06-at-09.31.35.png\")
<\/figure>\n
1-GS\/s TI-ADC for 5G baseband (2021)<\/strong><\/h3>\n\n\n\n1-GS\/s Time-Interleaved ADC in TSMC 28nm CMOS based on SAR ADC with on-chip digital calibration.<\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\n
Time-based boost converter with RHP zero elimination.<\/strong> (2020)<\/strong><\/h3>\n\n\n\nIntegrated boost converter with time-based control and RHP zero elimination in STM BCD8sp for AMOLED application.<\/p>\n<\/div>![\"\"](\"https:\/\/arplab.deib.polimi.it\/wp-content\/uploads\/2022\/02\/TBB-1.png\")
<\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
![\"\"](\"https:\/\/arplab.deib.polimi.it\/wp-content\/uploads\/2021\/10\/LOPS.png\")
<\/figure>\n12.9-to-15.1GHz PLL-Based LO Phase-Shifting System (2020)<\/strong><\/h3>\n\n\n\n12.9-to-15.1GHz LO-generation system prototype in TSMC 28nm CMOS based on a double bang-bang digital fractional-N PLL with a 19-bit resolution programmable phase shift between the two outputs. <\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\nA 14GHz Fast lock Bang-Bang Digital PLL (2019)<\/strong><\/h3>\n\n\n\nBang-bang digital PLL prototype in TSMC 28nm CMOS with 12.8-to-15.2-GHz output frequency range and a settling time below 20us .<\/p>\n<\/div>![\"\"](\"https:\/\/arplab.deib.polimi.it\/wp-content\/uploads\/2021\/11\/MicrosoftTeams-image-1024x608.png\")
<\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
![\"\"](\"https:\/\/arplab.deib.polimi.it\/wp-content\/uploads\/2021\/10\/lowj.png\")
<\/figure>\nA 12.5GHz Fractional-N Type-I Sampling PLL (2019)<\/strong><\/h3>\n\n\n\nAnalog sampling factional-N type-I PLL prototype in TSMC 28nm CMOS with 12.5-GHz output frequency, achieving 58fs of output signal integrated jitter.<\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\n20GHz Dual-Core Digital PLL<\/strong> (2018)<\/strong><\/h3>\n\n\n\nTwo-core bang-bang digital PLL prototype in STMicroelectronics 55nm BiCMOS process with second harmonic extraction and on-chip power combination.<\/p>\n<\/div>![\"\"](\"https:\/\/arplab.deib.polimi.it\/wp-content\/uploads\/2021\/10\/tar.png\")
<\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
![\"\"](\"https:\/\/arplab.deib.polimi.it\/wp-content\/uploads\/2021\/11\/MicrosoftTeams-image-1-1024x983.png\")
<\/figure>\n2.4GHz Digital MDLL (2017)<\/strong><\/h3>\n\n\n\nBang-bang sub-sampling digital MDLL prototype in TSMC 65nm CMOS with DTC range reduction technique at 2.5mW power consumption.<\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\n30-GHz Digital PLL (2017)<\/strong><\/h3>\n\n\n\nBang-bang sub-sampling digital PLL prototype in TSMC 65nm CMOS with 30GHz Oscillator, Injection Locking divider by 6, 5-GHz output frequency, and chirp modulation.<\/p>\n<\/div>![\"\"](\"https:\/\/arplab.deib.polimi.it\/wp-content\/uploads\/2021\/10\/30g.png\")
<\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
![\"\"](\"https:\/\/arplab.deib.polimi.it\/wp-content\/uploads\/2021\/10\/adpllv5.png\")
<\/figure>\n3.7-GHz Digital PLL<\/strong> (2016)<\/strong><\/h3>\n\n\n\nBang-bang digital PLL prototype in STM 65nm CMOS process with 3.7-GHz output frequency, fast frequency hopping, phase-noise level compliant with GSM requirements. [1]<\/a><\/p>\n<\/div><\/div>\n\n\n\n<\/p>\n","protected":false},"excerpt":{"rendered":"
List of designed, tested and published ASICs: 2-GS\/s TI-ADC for 5G baseband (2022) 2-GS\/s Time-Interleaved ADC in TSMC 28nm CMOS based on SAR ADC with on-chip digital calibration. Dual Mode buck converter (2022) Dual Mode buck converter with constant bandwidth … Continue reading
Dual Mode buck converter (2022)<\/strong><\/h3>\n\n\n\nDual Mode buck converter with constant bandwidth time-based control and 20uA quiescent current for industrial applications.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n
1-GS\/s TI-ADC for 5G baseband (2021)<\/strong><\/h3>\n\n\n\n1-GS\/s Time-Interleaved ADC in TSMC 28nm CMOS based on SAR ADC with on-chip digital calibration.<\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\n
Time-based boost converter with RHP zero elimination.<\/strong> (2020)<\/strong><\/h3>\n\n\n\nIntegrated boost converter with time-based control and RHP zero elimination in STM BCD8sp for AMOLED application.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n12.9-to-15.1GHz PLL-Based LO Phase-Shifting System (2020)<\/strong><\/h3>\n\n\n\n12.9-to-15.1GHz LO-generation system prototype in TSMC 28nm CMOS based on a double bang-bang digital fractional-N PLL with a 19-bit resolution programmable phase shift between the two outputs. <\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\nA 14GHz Fast lock Bang-Bang Digital PLL (2019)<\/strong><\/h3>\n\n\n\nBang-bang digital PLL prototype in TSMC 28nm CMOS with 12.8-to-15.2-GHz output frequency range and a settling time below 20us .<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\nA 12.5GHz Fractional-N Type-I Sampling PLL (2019)<\/strong><\/h3>\n\n\n\nAnalog sampling factional-N type-I PLL prototype in TSMC 28nm CMOS with 12.5-GHz output frequency, achieving 58fs of output signal integrated jitter.<\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\n20GHz Dual-Core Digital PLL<\/strong> (2018)<\/strong><\/h3>\n\n\n\nTwo-core bang-bang digital PLL prototype in STMicroelectronics 55nm BiCMOS process with second harmonic extraction and on-chip power combination.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n2.4GHz Digital MDLL (2017)<\/strong><\/h3>\n\n\n\nBang-bang sub-sampling digital MDLL prototype in TSMC 65nm CMOS with DTC range reduction technique at 2.5mW power consumption.<\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\n30-GHz Digital PLL (2017)<\/strong><\/h3>\n\n\n\nBang-bang sub-sampling digital PLL prototype in TSMC 65nm CMOS with 30GHz Oscillator, Injection Locking divider by 6, 5-GHz output frequency, and chirp modulation.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n3.7-GHz Digital PLL<\/strong> (2016)<\/strong><\/h3>\n\n\n\nBang-bang digital PLL prototype in STM 65nm CMOS process with 3.7-GHz output frequency, fast frequency hopping, phase-noise level compliant with GSM requirements. [1]<\/a><\/p>\n<\/div><\/div>\n\n\n\n<\/p>\n","protected":false},"excerpt":{"rendered":"
List of designed, tested and published ASICs: 2-GS\/s TI-ADC for 5G baseband (2022) 2-GS\/s Time-Interleaved ADC in TSMC 28nm CMOS based on SAR ADC with on-chip digital calibration. Dual Mode buck converter (2022) Dual Mode buck converter with constant bandwidth … Continue reading
<\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>
1-GS\/s TI-ADC for 5G baseband (2021)<\/strong><\/h3>\n\n\n\n1-GS\/s Time-Interleaved ADC in TSMC 28nm CMOS based on SAR ADC with on-chip digital calibration.<\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\n
Time-based boost converter with RHP zero elimination.<\/strong> (2020)<\/strong><\/h3>\n\n\n\nIntegrated boost converter with time-based control and RHP zero elimination in STM BCD8sp for AMOLED application.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n12.9-to-15.1GHz PLL-Based LO Phase-Shifting System (2020)<\/strong><\/h3>\n\n\n\n12.9-to-15.1GHz LO-generation system prototype in TSMC 28nm CMOS based on a double bang-bang digital fractional-N PLL with a 19-bit resolution programmable phase shift between the two outputs. <\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\nA 14GHz Fast lock Bang-Bang Digital PLL (2019)<\/strong><\/h3>\n\n\n\nBang-bang digital PLL prototype in TSMC 28nm CMOS with 12.8-to-15.2-GHz output frequency range and a settling time below 20us .<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\nA 12.5GHz Fractional-N Type-I Sampling PLL (2019)<\/strong><\/h3>\n\n\n\nAnalog sampling factional-N type-I PLL prototype in TSMC 28nm CMOS with 12.5-GHz output frequency, achieving 58fs of output signal integrated jitter.<\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\n20GHz Dual-Core Digital PLL<\/strong> (2018)<\/strong><\/h3>\n\n\n\nTwo-core bang-bang digital PLL prototype in STMicroelectronics 55nm BiCMOS process with second harmonic extraction and on-chip power combination.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n2.4GHz Digital MDLL (2017)<\/strong><\/h3>\n\n\n\nBang-bang sub-sampling digital MDLL prototype in TSMC 65nm CMOS with DTC range reduction technique at 2.5mW power consumption.<\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\n30-GHz Digital PLL (2017)<\/strong><\/h3>\n\n\n\nBang-bang sub-sampling digital PLL prototype in TSMC 65nm CMOS with 30GHz Oscillator, Injection Locking divider by 6, 5-GHz output frequency, and chirp modulation.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n3.7-GHz Digital PLL<\/strong> (2016)<\/strong><\/h3>\n\n\n\nBang-bang digital PLL prototype in STM 65nm CMOS process with 3.7-GHz output frequency, fast frequency hopping, phase-noise level compliant with GSM requirements. [1]<\/a><\/p>\n<\/div><\/div>\n\n\n\n<\/p>\n","protected":false},"excerpt":{"rendered":"
List of designed, tested and published ASICs: 2-GS\/s TI-ADC for 5G baseband (2022) 2-GS\/s Time-Interleaved ADC in TSMC 28nm CMOS based on SAR ADC with on-chip digital calibration. Dual Mode buck converter (2022) Dual Mode buck converter with constant bandwidth … Continue reading
Time-based boost converter with RHP zero elimination.<\/strong> (2020)<\/strong><\/h3>\n\n\n\nIntegrated boost converter with time-based control and RHP zero elimination in STM BCD8sp for AMOLED application.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n12.9-to-15.1GHz PLL-Based LO Phase-Shifting System (2020)<\/strong><\/h3>\n\n\n\n12.9-to-15.1GHz LO-generation system prototype in TSMC 28nm CMOS based on a double bang-bang digital fractional-N PLL with a 19-bit resolution programmable phase shift between the two outputs. <\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\nA 14GHz Fast lock Bang-Bang Digital PLL (2019)<\/strong><\/h3>\n\n\n\nBang-bang digital PLL prototype in TSMC 28nm CMOS with 12.8-to-15.2-GHz output frequency range and a settling time below 20us .<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\nA 12.5GHz Fractional-N Type-I Sampling PLL (2019)<\/strong><\/h3>\n\n\n\nAnalog sampling factional-N type-I PLL prototype in TSMC 28nm CMOS with 12.5-GHz output frequency, achieving 58fs of output signal integrated jitter.<\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\n20GHz Dual-Core Digital PLL<\/strong> (2018)<\/strong><\/h3>\n\n\n\nTwo-core bang-bang digital PLL prototype in STMicroelectronics 55nm BiCMOS process with second harmonic extraction and on-chip power combination.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n2.4GHz Digital MDLL (2017)<\/strong><\/h3>\n\n\n\nBang-bang sub-sampling digital MDLL prototype in TSMC 65nm CMOS with DTC range reduction technique at 2.5mW power consumption.<\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\n30-GHz Digital PLL (2017)<\/strong><\/h3>\n\n\n\nBang-bang sub-sampling digital PLL prototype in TSMC 65nm CMOS with 30GHz Oscillator, Injection Locking divider by 6, 5-GHz output frequency, and chirp modulation.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n3.7-GHz Digital PLL<\/strong> (2016)<\/strong><\/h3>\n\n\n\nBang-bang digital PLL prototype in STM 65nm CMOS process with 3.7-GHz output frequency, fast frequency hopping, phase-noise level compliant with GSM requirements. [1]<\/a><\/p>\n<\/div><\/div>\n\n\n\n<\/p>\n","protected":false},"excerpt":{"rendered":"
List of designed, tested and published ASICs: 2-GS\/s TI-ADC for 5G baseband (2022) 2-GS\/s Time-Interleaved ADC in TSMC 28nm CMOS based on SAR ADC with on-chip digital calibration. Dual Mode buck converter (2022) Dual Mode buck converter with constant bandwidth … Continue reading
<\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>12.9-to-15.1GHz PLL-Based LO Phase-Shifting System (2020)<\/strong><\/h3>\n\n\n\n12.9-to-15.1GHz LO-generation system prototype in TSMC 28nm CMOS based on a double bang-bang digital fractional-N PLL with a 19-bit resolution programmable phase shift between the two outputs. <\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\nA 14GHz Fast lock Bang-Bang Digital PLL (2019)<\/strong><\/h3>\n\n\n\nBang-bang digital PLL prototype in TSMC 28nm CMOS with 12.8-to-15.2-GHz output frequency range and a settling time below 20us .<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\nA 12.5GHz Fractional-N Type-I Sampling PLL (2019)<\/strong><\/h3>\n\n\n\nAnalog sampling factional-N type-I PLL prototype in TSMC 28nm CMOS with 12.5-GHz output frequency, achieving 58fs of output signal integrated jitter.<\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\n20GHz Dual-Core Digital PLL<\/strong> (2018)<\/strong><\/h3>\n\n\n\nTwo-core bang-bang digital PLL prototype in STMicroelectronics 55nm BiCMOS process with second harmonic extraction and on-chip power combination.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n2.4GHz Digital MDLL (2017)<\/strong><\/h3>\n\n\n\nBang-bang sub-sampling digital MDLL prototype in TSMC 65nm CMOS with DTC range reduction technique at 2.5mW power consumption.<\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\n30-GHz Digital PLL (2017)<\/strong><\/h3>\n\n\n\nBang-bang sub-sampling digital PLL prototype in TSMC 65nm CMOS with 30GHz Oscillator, Injection Locking divider by 6, 5-GHz output frequency, and chirp modulation.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n3.7-GHz Digital PLL<\/strong> (2016)<\/strong><\/h3>\n\n\n\nBang-bang digital PLL prototype in STM 65nm CMOS process with 3.7-GHz output frequency, fast frequency hopping, phase-noise level compliant with GSM requirements. [1]<\/a><\/p>\n<\/div><\/div>\n\n\n\n<\/p>\n","protected":false},"excerpt":{"rendered":"
List of designed, tested and published ASICs: 2-GS\/s TI-ADC for 5G baseband (2022) 2-GS\/s Time-Interleaved ADC in TSMC 28nm CMOS based on SAR ADC with on-chip digital calibration. Dual Mode buck converter (2022) Dual Mode buck converter with constant bandwidth … Continue reading
A 14GHz Fast lock Bang-Bang Digital PLL (2019)<\/strong><\/h3>\n\n\n\nBang-bang digital PLL prototype in TSMC 28nm CMOS with 12.8-to-15.2-GHz output frequency range and a settling time below 20us .<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\nA 12.5GHz Fractional-N Type-I Sampling PLL (2019)<\/strong><\/h3>\n\n\n\nAnalog sampling factional-N type-I PLL prototype in TSMC 28nm CMOS with 12.5-GHz output frequency, achieving 58fs of output signal integrated jitter.<\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\n20GHz Dual-Core Digital PLL<\/strong> (2018)<\/strong><\/h3>\n\n\n\nTwo-core bang-bang digital PLL prototype in STMicroelectronics 55nm BiCMOS process with second harmonic extraction and on-chip power combination.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n2.4GHz Digital MDLL (2017)<\/strong><\/h3>\n\n\n\nBang-bang sub-sampling digital MDLL prototype in TSMC 65nm CMOS with DTC range reduction technique at 2.5mW power consumption.<\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\n30-GHz Digital PLL (2017)<\/strong><\/h3>\n\n\n\nBang-bang sub-sampling digital PLL prototype in TSMC 65nm CMOS with 30GHz Oscillator, Injection Locking divider by 6, 5-GHz output frequency, and chirp modulation.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n3.7-GHz Digital PLL<\/strong> (2016)<\/strong><\/h3>\n\n\n\nBang-bang digital PLL prototype in STM 65nm CMOS process with 3.7-GHz output frequency, fast frequency hopping, phase-noise level compliant with GSM requirements. [1]<\/a><\/p>\n<\/div><\/div>\n\n\n\n<\/p>\n","protected":false},"excerpt":{"rendered":"
List of designed, tested and published ASICs: 2-GS\/s TI-ADC for 5G baseband (2022) 2-GS\/s Time-Interleaved ADC in TSMC 28nm CMOS based on SAR ADC with on-chip digital calibration. Dual Mode buck converter (2022) Dual Mode buck converter with constant bandwidth … Continue reading
<\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>A 12.5GHz Fractional-N Type-I Sampling PLL (2019)<\/strong><\/h3>\n\n\n\nAnalog sampling factional-N type-I PLL prototype in TSMC 28nm CMOS with 12.5-GHz output frequency, achieving 58fs of output signal integrated jitter.<\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\n20GHz Dual-Core Digital PLL<\/strong> (2018)<\/strong><\/h3>\n\n\n\nTwo-core bang-bang digital PLL prototype in STMicroelectronics 55nm BiCMOS process with second harmonic extraction and on-chip power combination.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n2.4GHz Digital MDLL (2017)<\/strong><\/h3>\n\n\n\nBang-bang sub-sampling digital MDLL prototype in TSMC 65nm CMOS with DTC range reduction technique at 2.5mW power consumption.<\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\n30-GHz Digital PLL (2017)<\/strong><\/h3>\n\n\n\nBang-bang sub-sampling digital PLL prototype in TSMC 65nm CMOS with 30GHz Oscillator, Injection Locking divider by 6, 5-GHz output frequency, and chirp modulation.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n3.7-GHz Digital PLL<\/strong> (2016)<\/strong><\/h3>\n\n\n\nBang-bang digital PLL prototype in STM 65nm CMOS process with 3.7-GHz output frequency, fast frequency hopping, phase-noise level compliant with GSM requirements. [1]<\/a><\/p>\n<\/div><\/div>\n\n\n\n<\/p>\n","protected":false},"excerpt":{"rendered":"
List of designed, tested and published ASICs: 2-GS\/s TI-ADC for 5G baseband (2022) 2-GS\/s Time-Interleaved ADC in TSMC 28nm CMOS based on SAR ADC with on-chip digital calibration. Dual Mode buck converter (2022) Dual Mode buck converter with constant bandwidth … Continue reading
20GHz Dual-Core Digital PLL<\/strong> (2018)<\/strong><\/h3>\n\n\n\nTwo-core bang-bang digital PLL prototype in STMicroelectronics 55nm BiCMOS process with second harmonic extraction and on-chip power combination.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n2.4GHz Digital MDLL (2017)<\/strong><\/h3>\n\n\n\nBang-bang sub-sampling digital MDLL prototype in TSMC 65nm CMOS with DTC range reduction technique at 2.5mW power consumption.<\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\n30-GHz Digital PLL (2017)<\/strong><\/h3>\n\n\n\nBang-bang sub-sampling digital PLL prototype in TSMC 65nm CMOS with 30GHz Oscillator, Injection Locking divider by 6, 5-GHz output frequency, and chirp modulation.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n3.7-GHz Digital PLL<\/strong> (2016)<\/strong><\/h3>\n\n\n\nBang-bang digital PLL prototype in STM 65nm CMOS process with 3.7-GHz output frequency, fast frequency hopping, phase-noise level compliant with GSM requirements. [1]<\/a><\/p>\n<\/div><\/div>\n\n\n\n<\/p>\n","protected":false},"excerpt":{"rendered":"
List of designed, tested and published ASICs: 2-GS\/s TI-ADC for 5G baseband (2022) 2-GS\/s Time-Interleaved ADC in TSMC 28nm CMOS based on SAR ADC with on-chip digital calibration. Dual Mode buck converter (2022) Dual Mode buck converter with constant bandwidth … Continue reading
<\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>2.4GHz Digital MDLL (2017)<\/strong><\/h3>\n\n\n\nBang-bang sub-sampling digital MDLL prototype in TSMC 65nm CMOS with DTC range reduction technique at 2.5mW power consumption.<\/p>\n<\/div><\/div>\n\n\n\n
<\/p>\n\n\n\n
\n30-GHz Digital PLL (2017)<\/strong><\/h3>\n\n\n\nBang-bang sub-sampling digital PLL prototype in TSMC 65nm CMOS with 30GHz Oscillator, Injection Locking divider by 6, 5-GHz output frequency, and chirp modulation.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n3.7-GHz Digital PLL<\/strong> (2016)<\/strong><\/h3>\n\n\n\nBang-bang digital PLL prototype in STM 65nm CMOS process with 3.7-GHz output frequency, fast frequency hopping, phase-noise level compliant with GSM requirements. [1]<\/a><\/p>\n<\/div><\/div>\n\n\n\n<\/p>\n","protected":false},"excerpt":{"rendered":"
List of designed, tested and published ASICs: 2-GS\/s TI-ADC for 5G baseband (2022) 2-GS\/s Time-Interleaved ADC in TSMC 28nm CMOS based on SAR ADC with on-chip digital calibration. Dual Mode buck converter (2022) Dual Mode buck converter with constant bandwidth … Continue reading
30-GHz Digital PLL (2017)<\/strong><\/h3>\n\n\n\nBang-bang sub-sampling digital PLL prototype in TSMC 65nm CMOS with 30GHz Oscillator, Injection Locking divider by 6, 5-GHz output frequency, and chirp modulation.<\/p>\n<\/div><\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>\n3.7-GHz Digital PLL<\/strong> (2016)<\/strong><\/h3>\n\n\n\nBang-bang digital PLL prototype in STM 65nm CMOS process with 3.7-GHz output frequency, fast frequency hopping, phase-noise level compliant with GSM requirements. [1]<\/a><\/p>\n<\/div><\/div>\n\n\n\n<\/p>\n","protected":false},"excerpt":{"rendered":"
List of designed, tested and published ASICs: 2-GS\/s TI-ADC for 5G baseband (2022) 2-GS\/s Time-Interleaved ADC in TSMC 28nm CMOS based on SAR ADC with on-chip digital calibration. Dual Mode buck converter (2022) Dual Mode buck converter with constant bandwidth … Continue reading
<\/figure><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/figure>3.7-GHz Digital PLL<\/strong> (2016)<\/strong><\/h3>\n\n\n\nBang-bang digital PLL prototype in STM 65nm CMOS process with 3.7-GHz output frequency, fast frequency hopping, phase-noise level compliant with GSM requirements. [1]<\/a><\/p>\n<\/div><\/div>\n\n\n\n<\/p>\n","protected":false},"excerpt":{"rendered":"
List of designed, tested and published ASICs: 2-GS\/s TI-ADC for 5G baseband (2022) 2-GS\/s Time-Interleaved ADC in TSMC 28nm CMOS based on SAR ADC with on-chip digital calibration. Dual Mode buck converter (2022) Dual Mode buck converter with constant bandwidth … Continue reading
<\/p>\n","protected":false},"excerpt":{"rendered":"
List of designed, tested and published ASICs: 2-GS\/s TI-ADC for 5G baseband (2022) 2-GS\/s Time-Interleaved ADC in TSMC 28nm CMOS based on SAR ADC with on-chip digital calibration. Dual Mode buck converter (2022) Dual Mode buck converter with constant bandwidth … Continue reading