{"id":15,"date":"2021-07-07T20:00:36","date_gmt":"2021-07-07T20:00:36","guid":{"rendered":"https:\/\/arplab.deib.polimi.it\/?page_id=15"},"modified":"2024-01-31T20:48:40","modified_gmt":"2024-01-31T20:48:40","slug":"thesis","status":"publish","type":"page","link":"https:\/\/arplab.deib.polimi.it\/?page_id=15","title":{"rendered":"Thesis Opportunities"},"content":{"rendered":"\n

Join our research group! <\/strong><\/p>\n\n\n\n

Here the list of available thesis topics during the A.A. 2023\/2024<\/strong><\/p>\n\n\n\n

Further thesis topics will be published soon…<\/p>\n\n\n\n

Thesis topics with the [#]<\/strong> flag are not more available<\/p>\n\n\n\n

ADC research group:<\/strong><\/h2>\n\n\n\n

Baseband<\/em><\/strong> ADC system design<\/em><\/strong><\/p>\n\n\n\n

    \n
  1. Exploration and system-level design of new hybrid ADC architectures for high-speed wireless<\/li>\n\n\n\n
  2. Digital equalisation of the frequency response in a multi-channel ADC<\/li>\n\n\n\n
  3. Low-power digital algorithms for ADC calibration and non-ideality correction<\/li>\n\n\n\n
  4. Design of a Software Defined Radio (SDR) receiver based on a custom prototype ADC<\/li>\n<\/ol>\n\n\n\n

    ADC circuit design<\/em><\/strong><\/p>\n\n\n\n

      \n
    1. Circuit design of a flash-type ADC with low power consumption and compact area<\/li>\n\n\n\n
    2. Circuit design of DAC with high linearity and low power consumption<\/li>\n\n\n\n
    3. Circuit design of a ring-type amplifier (Ring-Amp) [#]<\/strong><\/li>\n\n\n\n
    4. Design of Fully\/partial synthesizable of a fast synchronous\/asynchronous SAR logic<\/li>\n\n\n\n
    5. Circuit design of a bandgap reference in a 28-nm CMOS process<\/li>\n\n\n\n
    6. Circuit design of a Gbit\/s data interface<\/li>\n\n\n\n
    7. Design of on-chip low-jitter frequency synthesizer for high-speed ADCs.<\/li>\n<\/ol>\n\n\n\n

      More topics related to mixed-signal system and circuit design are also available upon request<\/em><\/p>\n\n\n\n

      RF research group<\/strong>:<\/h2>\n\n\n\n

      Transceiver\/Frequency Synthesizer system desig<\/em>n<\/strong>, RF & mmW circuit design<\/em><\/strong><\/p>\n\n\n\n

        \n
      1. Validation of a novel measurement method to obtain high resolution characteristics of digital-to-time converters and voltage-controlled oscillators. [NEW]<\/em><\/strong> <\/li>\n\n\n\n
      2. Fast frequency settling and convergence time techniques to minimize energy loss in Bluetooth Low Energy wake up transceivers. [NEW]<\/em><\/strong><\/li>\n\n\n\n
      3. System level architecture analysis for CMOS ultra-low-jitter phase locked loop for next 6G wireless backhaul applications. [NEW]<\/em><\/strong><\/li>\n\n\n\n
      4. Design of RF\/Mixed-Signal building blocks for CMOS ultra-low-jitter phase locked loop for next 6G wireless backhaul applications. [NEW]<\/em><\/strong><\/li>\n\n\n\n
      5. Implementation and measurement validation of real-time\u00a0digital\u00a0signal processing automotive FMCW radars systems. [NEW]<\/em><\/strong><\/li>\n\n\n\n
      6. Design of a crystal oscillator using energy-efficient techniques to maximize battery life in modern IoT radios. [NEW]<\/em><\/strong><\/li>\n\n\n\n
      7. Design of high linearity and high efficiency Wi-Fi 7 digital power-amplifier in CMOS scaled node. [NEW]<\/em><\/strong><\/li>\n\n\n\n
      8. Analysis of a digital phase locked loop architecture based on a novel phase detector topology for WLAN applications. [NEW]<\/em><\/strong><\/li>\n<\/ol>\n\n\n\n

        <\/p>\n\n\n\n

        PWR research group<\/strong>:<\/h2>\n\n\n\n
          \n
        1. Design of a 700W, 48V-to-3.4V resonant DC-DC converter for data-centers application. [NEW]<\/em><\/strong><\/li>\n\n\n\n
        2. Analysis and design of a phase shift control loop for quasi-resonant operation of a resonant DCDC converters.<\/li>\n\n\n\n
        3. Design of the power stage and driving network for an integrated 20MHz switching frequency 3-level hybrid buck converter. [NEW]<\/em><\/strong><\/li>\n\n\n\n
        4. Design of a novel control network with flying capacitor voltage regulation for an integrated 20MHz switching frequency 3-level hybrid buck converter. [NEW]<\/em><\/strong><\/li>\n\n\n\n
        5. VCO control for variable frequency operation in an integrated buck converter with peak-current control (Thesis in collaboration with STMicroelectronics) [NEW]<\/em><\/strong><\/li>\n<\/ol>\n\n\n\n

          <\/p>\n","protected":false},"excerpt":{"rendered":"

          Join our research group! Here the list of available thesis topics during the A.A. 2023\/2024 Further thesis topics will be published soon… Thesis topics with the [#] flag are not more available ADC research group: Baseband ADC system design ADC … Continue reading →<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"parent":0,"menu_order":7,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-15","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/arplab.deib.polimi.it\/index.php?rest_route=\/wp\/v2\/pages\/15","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/arplab.deib.polimi.it\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/arplab.deib.polimi.it\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/arplab.deib.polimi.it\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/arplab.deib.polimi.it\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=15"}],"version-history":[{"count":15,"href":"https:\/\/arplab.deib.polimi.it\/index.php?rest_route=\/wp\/v2\/pages\/15\/revisions"}],"predecessor-version":[{"id":518,"href":"https:\/\/arplab.deib.polimi.it\/index.php?rest_route=\/wp\/v2\/pages\/15\/revisions\/518"}],"wp:attachment":[{"href":"https:\/\/arplab.deib.polimi.it\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=15"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}