{"id":11,"date":"2021-07-07T19:59:12","date_gmt":"2021-07-07T19:59:12","guid":{"rendered":"https:\/\/arplab.deib.polimi.it\/?page_id=11"},"modified":"2026-02-14T14:53:52","modified_gmt":"2026-02-14T14:53:52","slug":"publications","status":"publish","type":"page","link":"https:\/\/arplab.deib.polimi.it\/?page_id=11","title":{"rendered":"Publications"},"content":{"rendered":"\n

2026<\/h2>\n\n\n\n

…<\/p>\n\n\n\n

2025<\/h2>\n\n\n\n

I. Ferrari, G. Zanoletti, L. Bertulessi, A. L. Lacaita, C. Samori and A. Bonfanti, “An Analysis of Switch Thermal Noise in SAR Converters<\/strong>,” in IEEE Transactions on Circuits and Systems II: Express Briefs<\/em>, doi: 10.1109\/TCSII.2025.3622315.<\/p>\n\n\n\n

A. Ceroni, G. Zanoletti, E. Albezzano, A. G. Bonfanti and C. Samori, “A Complementary Bootstrapped Sampler for High-Frequency High-Resolution ADCs,<\/strong>” 2025 International Conference on IC Design and Technology (ICICDT)<\/em>, Lecce, Italy, 2025, pp. 137-140, doi: 10.1109\/ICICDT65192.2025.11078100.<\/p>\n\n\n\n

G. Tombolan, C. Samori, A. Bonfanti and L. Bertulessi, “Power-Reduction Technique for Time-to-Digital Converters in 28-nm CMOS Process<\/strong>,” 2025 International Conference on IC Design and Technology (ICICDT)<\/em>, Lecce, Italy, 2025, pp. 141-144, doi: 10.1109\/ICICDT65192.2025.11078080.<\/p>\n\n\n\n

G. Zanoletti et al<\/em>., “A 20MHz-BW 12.3-ENOB NS SAR ADC with a 3rd-order Multi-Input Filter and a PVT-Robust Ratio-Based FIA<\/strong>,” 2025 IEEE Custom Integrated Circuits Conference (CICC)<\/em>, Boston, MA, USA, 2025, pp. 1-3, doi: 10.1109\/CICC63670.2025.10983265.<\/p>\n\n\n\n

G. Castoro et al<\/em>., “A Low-Jitter Fractional-N Digital PLL With Spur Cancellation Based on a Multi-DTC Topology<\/strong>,” in IEEE Journal of Solid-State Circuits<\/em>, doi: 10.1109\/JSSC.2025.3560870.<\/p>\n\n\n\n

S. M. Dartizio et al<\/em>., “34.2 A 380\u03bcW and \u2212242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20\u03bcs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS,<\/strong>” 2025 IEEE International Solid-State Circuits Conference (ISSCC)<\/em>, San Francisco, CA, USA, 2025, pp. 1-3, doi: 10.1109\/ISSCC49661.2025.10904691.<\/p>\n\n\n\n

S. Gallucci et al<\/em>., “34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning,<\/strong>” 2025 IEEE International Solid-State Circuits Conference (ISSCC)<\/em>, San Francisco, CA, USA, 2025, pp. 558-560, doi: 10.1109\/ISSCC49661.2025.10904710.<\/p>\n\n\n\n

2024<\/h2>\n\n\n\n

M. Rossoni et al., “A Low-Jitter Fractional-N Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC,<\/strong>” in IEEE Journal of Solid-State Circuits, doi: 10.1109\/JSSC.2024.3469556.<\/p>\n\n\n\n

F. Tesolin et al., “A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars,<\/strong>” in IEEE Journal of Solid-State Circuits, doi: 10.1109\/JSSC.2024.3460178.<\/p>\n\n\n\n

R. Moleri et al., “A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique,<\/strong>” 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2024, pp. 1-2, doi: 10.1109\/VLSITechnologyandCir46783.2024.10631343.<\/p>\n\n\n\n

P. Salvi et al., “A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC<\/strong>,” 2024 IEEE Custom Integrated Circuits Conference (CICC), Denver, CO, USA, 2024, pp. 1-2, doi: 10.1109\/CICC60959.2024.10529003.<\/p>\n\n\n\n

S. M. Dartizio et al., “A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector<\/strong>,” 2024 IEEE Custom Integrated Circuits Conference (CICC), Denver, CO, USA, 2024, pp. 1-2, doi: 10.1109\/CICC60959.2024.10529002.<\/p>\n\n\n\n

L. Ricci et al<\/em>., “A 2-GS\/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk<\/strong>,” in IEEE Journal of Solid-State Circuits<\/em>, doi: 10.1109\/JSSC.2024.3437168.<\/p>\n\n\n\n

A. Ceroni, G. Zanoletti, A. Bonfanti and C. Samori, “A Highly Energy-Efficient FIA-based AZ-free Ring Amplifier for Pipeline-SAR ADCs,<\/strong>” 2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)<\/em>, Larnaca, Cyprus, 2024, pp. 1-4, doi: 10.1109\/PRIME61930.2024.10559719.<\/p>\n\n\n\n

P. Melillo, M. Leoncini, S. Levantino and M. Ghioni, “Insights on the Dynamic Performance of Nonminimum-Phase Boost Converters Exploiting Inductor-Current-Feedback RHPZ Mitigation,<\/strong>” in IEEE Transactions on Power Electronics<\/em>, vol. 39, no. 4, pp. 4160-4172, April 2024, doi: 10.1109\/TPEL.2024.3352275.<\/p>\n\n\n\n

P. Melillo et al<\/em>., “A Wide-Input-Range Time-Based Buck Converter With Adaptive Gain and Continuous Phase Preset for Seamless PFM\/PWM Transitions<\/strong>,” in IEEE Transactions on Circuits and Systems I: Regular Papers<\/em>, doi: 10.1109\/TCSI.2024.3371969.<\/p>\n\n\n\n

A. Dago et al<\/em>., “A High-Power-Density Quasi-Resonant Switched-Capacitor DC\u2013DC Converter With Single Semiperiod Tank Current Modulation<\/strong>,” in IEEE Transactions on Power Electronics<\/em>, vol. 39, no. 2, pp. 2100-2114, Feb. 2024, doi: 10.1109\/TPEL.2023.3333696.<\/p>\n\n\n\n

M. Rossoni et al., “An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and \u2212252.4dB FoM,<\/strong>” 2024 IEEE International Solid-State Circuits Conference (ISSCC)<\/em>, San Francisco, CA, USA, 2024, pp. 188-190, doi: 10.1109\/ISSCC49657.2024.10454388.<\/p>\n\n\n\n

F. Tesolin et al., “A 10GHz FMCW Modulator Achieving 680MHz\/\u03bcs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion,<\/strong>” 2024 IEEE International Solid-State Circuits Conference (ISSCC)<\/em>, San Francisco, CA, USA, 2024, pp. 198-200, doi: 10.1109\/ISSCC49657.2024.10454289.<\/p>\n\n\n\n

A. Bertolini, M. Leoncini, P. Melillo, A. Gasparini, S. Levantino and M. Ghioni, “A 1-A 90% Peak Efficiency 5\u201336\u2009V Input Voltage Time-Based Buck Converter With Adaptive Gain Compensation and Controlled-Skip Operation,<\/strong>” in IEEE Transactions on Power Electronics<\/em>, vol. 39, no. 1, pp. 973-984, Jan. 2024, doi: 10.1109\/TPEL.2023.3320354. <\/p>\n\n\n\n

G. Zanoletti et al<\/em>., “A 250-MS\/s 9.9-ENOB 80.7 dB-SFDR Top-Plate Input SAR ADC With Charge Linearization,<\/strong>” in IEEE Transactions on Circuits and Systems II: Express Briefs<\/em>, vol. 71, no. 3, pp. 1551-1555, March 2024, doi: 10.1109\/TCSII.2023.3336943. <\/p>\n\n\n\n

2023<\/h2>\n\n\n\n

S. M. Dartizio et al., “A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering,<\/strong>” in IEEE Journal of Solid-State Circuits<\/em>, vol. 58, no. 12, pp. 3320-3337, Dec. 2023, doi: 10.1109\/JSSC.2023.3311681. <\/p>\n\n\n\n

P. Melillo et al<\/em>., “A Compact Wide-Input-Range Time-Domain Buck Converter with Fast Transient Response for Industrial Applications<\/strong>,” ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)<\/em>, Lisbon, Portugal, 2023, pp. 433-436, doi: 10.1109\/ESSCIRC59616.2023.10268695.<\/p>\n\n\n\n

F. Tesolin et al<\/em>., “A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays<\/strong>,” in IEEE Journal of Solid-State Circuits<\/em>, vol. 58, no. 9, pp. 2466-2477, Sept. 2023, doi: 10.1109\/JSSC.2023.3272483.<\/p>\n\n\n\n

P. Melillo, S. Zaffin, A. Gasparini, S. Levantino and M. Ghioni, “Time-Based Buck Converter with Variable Frequency DCM and ON-Time Correction for Seamless Transitions<\/strong>,” 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)<\/em>, Valencia, Spain, 2023, pp. 205-208, doi: 10.1109\/PRIME58259.2023.10161753.<\/p>\n\n\n\n

S. Zaffin, S. Macario, A. Bertolini, M. Leoncini and M. Ghioni, “Common-Gate Zero Current Detector with Body-Voltage Based Offset Compensation<\/strong>,” 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)<\/em>, Valencia, Spain, 2023, pp. 353-356, doi: 10.1109\/PRIME58259.2023.10161872.<\/p>\n\n\n\n

L. Ricci et al<\/em>., “A 2GS\/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS,<\/strong>” 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)<\/em>, Kyoto, Japan, 2023, pp. 1-2, doi: 10.23919\/VLSITechnologyandCir57934.2023.10185370.<\/p>\n\n\n\n

L. Scaletti, L. Bertulessi, A. Cristofoli and A. Bonfanti, “A Novel Push-Pull Input Buffer for Wideband ADCs with Improved High-Frequency Linearity,<\/strong>” 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS)<\/em>, Edinburgh, United Kingdom, 2023, pp. 1-5, doi: 10.1109\/NEWCAS57931.2023.10198057.<\/p>\n\n\n\n

M. Leoncini, A. Dago, A. Bertolini, A. Gasparini, S. Levantino and M. Ghioni, “A Compact High-Efficiency Boost Converter With Time-Based Control, RHP Zero-Elimination, and Tracking Error Compensation,<\/strong>” in IEEE Transactions on Power Electronics<\/em>, vol. 38, no. 3, pp. 3100-3113, March 2023, doi: 10.1109\/TPEL.2022.3222613. <\/p>\n\n\n\n

M. Leoncini, A. Bertolini, P. Melillo, A. Gasparini, S. Levantino and M. Ghioni, “Spread-Spectrum Frequency Modulation in a DC\/DC Converter With Time-Based Control,<\/strong>” in IEEE Transactions on Power Electronics<\/em>, vol. 38, no. 4, pp. 4207-4211, April 2023, doi: 10.1109\/TPEL.2022.3227954.<\/p>\n\n\n\n

A. Dago et al<\/em>., “High Power Density 4:1 Resonant Switched-Capacitor DC-DC Converter for PoL Applications,<\/strong>” 2023 IEEE Applied Power Electronics Conference and Exposition (APEC)<\/em>, Orlando, FL, USA, 2023, pp. 926-931, doi: 10.1109\/APEC43580.2023.10131514.<\/p>\n\n\n\n

F. Buccoleri et al<\/em>., “A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner<\/strong>,” in IEEE Journal of Solid-State Circuits<\/em>, vol. 58, no. 3, pp. 634-646, March 2023, doi: 10.1109\/JSSC.2022.3228899.<\/p>\n\n\n\n

G. Castoro et al<\/em>., “4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology<\/strong>,” 2023 IEEE International Solid- State Circuits Conference (ISSCC)<\/em>, San Francisco, CA, USA, 2023, pp. 82-84, doi: 10.1109\/ISSCC42615.2023.10067351.<\/p>\n\n\n\n

S. M. Dartizio et al<\/em>., “4.3 A 76.7fs-lntegrated-Jitter and \u221271.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering<\/strong>,” 2023 IEEE International Solid- State Circuits Conference (ISSCC)<\/em>, San Francisco, CA, USA, 2023, pp. 3-5, doi: 10.1109\/ISSCC42615.2023.10067719.<\/p>\n\n\n\n

G. Castoro, S. M. Dartizio, A. L. Lacaita and S. Levantino, “Phase Noise Analysis of Periodically ON\/OFF Switched Oscillators,<\/strong>” in IEEE Transactions on Circuits and Systems I: Regular Papers<\/em>, vol. 70, no. 1, pp. 54-63, Jan. 2023, doi: 10.1109\/TCSI.2022.3211177.<\/p>\n\n\n\n

2022<\/h2>\n\n\n\n

S. M. Dartizio et al<\/em>., “A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 \u03bcs-Locking-Time<\/strong>,” in IEEE Journal of Solid-State Circuits<\/em>, vol. 57, no. 12, pp. 3538-3551, Dec. 2022, doi: 10.1109\/JSSC.2022.3206955<\/p>\n\n\n\n

S. M. Dartizio et al<\/em>., “A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping<\/strong>,” in IEEE Journal of Solid-State Circuits<\/em>, vol. 57, no. 6, pp. 1723-1735, June 2022, doi: 10.1109\/JSSC.2021.3116860.<\/p>\n\n\n\n

A. Dago, M. Leoncini, S. Saggini, S. Levantino and M. Ghioni, “Hybrid Resonant Switched-Capacitor Converter for 48\u20133.4 V Direct Conversion<\/strong>,” in IEEE Transactions on Power Electronics, vol. 37, no. 11, pp. 12998-13002, Nov. 2022, doi: 10.1109\/TPEL.2022.3186790. [URL<\/a>]<\/p>\n\n\n\n

M. Leoncini, P. Melillo, A. Bertolini, S. Levantino and M. Ghioni, “Integrated Loop-Gain Measurement Circuit for DC\/DC Boost Converters with Time-Based Control<\/strong>,” 2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2022, pp. 253-256, doi: 10.1109\/PRIME55000.2022.9816761. [URL<\/a>]<\/p>\n\n\n\n

A. Dago, M. Leoncini, A. Cattani, S. Levantino and M. Ghioni, “A Novel Common-Gate Comparator with Auto-Zeroing Offset Cancellation,<\/strong>” 2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)<\/em>, 2022, pp. 81-84, doi: 10.1109\/PRIME55000.2022.9816755. [URL<\/a>]<\/p>\n\n\n\n

P. Melillo, A. Dago, A. Gasparini, S. Levantino and M. Ghioni, “A Novel Feedforward Technique for Improved Line Transient in Time-Based-Controlled Boost Converters,”<\/strong> 2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2022, pp. 257-260, doi: 10.1109\/PRIME55000.2022.9816834. [URL<\/a>]<\/p>\n\n\n\n

G. B\u00e8, A.Parisi, L. Bertulessi, L. Ricci, L. Scaletti, M. Mercandelli, A.L. Lacaita, S. Levantino, C.Samori, A. Bonfanti , “A 900-MS\/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations<\/strong>,” in IEEE Transactions on Circuits and Systems II: Express Briefs<\/em>, 2022, doi: 10.1109\/TCSII.2022.3182217. [URL<\/a>]<\/p>\n\n\n\n

A. Garghetti, A. L. Lacaita, D. Seebacher, M. Bassi and S. Levantino, “Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology<\/strong>,” in IEEE Journal of Solid-State Circuits<\/em>, vol. 57, no. 6, pp. 1788-1799, June 2022, doi: 10.1109\/JSSC.2021.3134486.[URL<\/a>]<\/p>\n\n\n\n

M. Mercandelli, L. Bertulessi, C. Samori and S. Levantino, “A Digital PLL With Multitap LMS-Based Bandwidth Control<\/strong>,” in IEEE Solid-State Circuits Letters<\/em>, vol. 5, pp. 126-129, 2022, doi: 10.1109\/LSSC.2022.3173425. [URL]<\/a><\/p>\n\n\n\n

F.Buccoleri, S.M. Dartizio, F. Tesolin, L. Avallone, A. Santiccioli, A. Lesurum, G. Steffan, A. Bevilacqua, L. Bertulessi, D. Cherniak, C. Samori, A.L. Lacaita, S. Levantino, “A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler<\/strong>,” 2022 IEEE Custom Integrated Circuits Conference (CICC)<\/em>, 2022, pp. 1-2, doi: 10.1109\/CICC53496.2022.9772796. [URL<\/a>]<\/p>\n\n\n\n

S.M. Dartizio, F. Buccoleri, F. Tesolin, L.  Avallone, A. Santiccioli, A. Iesurum, G. Steffan, Giovanni, D. Cherniak, L. Bertulessi, A. Bevilacqua, C. Samori, A.L. Lacaita, S. Levantino, “A 68.6fsrms<\/sub>-total-integrated-jitter and 1.56\u03bcs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching<\/strong>,” 2022 IEEE International Solid- State Circuits Conference (ISSCC)<\/em>, 2022, pp. 1-3, doi: 10.1109\/ISSCC42614.2022.9731683. [URL<\/a>]<\/p>\n\n\n\n

L. Bertulessi, D. Cherniak, M. Mercandelli, C. Samori, A. L. Lacaita and S. Levantino, “Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise<\/strong>,” in IEEE Transactions on Circuits and Systems I: Regular Papers, doi: 10.1109\/TCSI.2022.3146788. [URL]<\/a><\/p>\n\n\n\n

2021<\/h2>\n\n\n\n

M. Leoncini, A. Bertolini, A. Gasparini, S. Levantino and M. Ghioni, “An 800-mA Time-Based Boost Converter in 0.18\u00b5m BCD with Right-Half-Plane Zero Elimination and 96% Power Efficiency<\/strong>,” ESSCIRC 2021 – IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, pp. 223-226, doi: 10.1109\/ESSCIRC53450.2021.9567838. [URL]<\/a><\/p>\n\n\n\n

L. Ricci, L. Bertulessi and A. Bonfanti, “A low-noise high-speed comparator for a 12-bit 200-MSps SAR ADC in a 28-nm CMOS process<\/strong>,” SMACD \/ PRIME 2021; International Conference on SMACD and 16th Conference on PRIME<\/em>, online, 2021, pp. 1-4. [URL<\/a>]<\/p>\n\n\n\n

G. Be, M. Mercandelli and L. Bertulessi, “A Timing Skew Correction Technique in Time-Interleaved ADCs Based on a DeltaSigma Digital-to-Time Converter,<\/strong>” SMACD \/ PRIME 2021; International Conference on SMACD and 16th Conference on PRIME<\/em>, online, 2021, pp. 1-4. [URL]<\/a><\/p>\n\n\n\n

L. Scaletti, A. Parisi and L. Bertulessi, “Skew and Jitter Performance in CMOS Clock Phase Splitter Circuits,<\/strong>” SMACD \/ PRIME 2021; International Conference on SMACD and 16th Conference on PRIME<\/em>, online, 2021, pp. 1-4. [URL]<\/a><\/p>\n\n\n\n

A. Parisi, F. Tesolin, M. Mercandelli, L. Bertulessi and A. L. Lacaita, “Self-Biasing Dynamic Start-up Circuit for Current-Biased Class-C Oscillators<\/strong>,” in IEEE Microwave and Wireless Components Letters, doi: 10.1109\/LMWC.2021.3094418. [URL<\/a>]<\/p>\n\n\n\n

F. Buccoleri, A. Bonfanti and A. L. Lacaita, “A Generalization of the Groszkowski\u2019s Result in Differential Oscillator Topologies<\/strong>,” in IEEE Transactions on Circuits and Systems I: Regular Papers<\/em>, vol. 68, no. 7, pp. 2800-2812, July 2021. doi: 10.1109\/TCSI.2021.3077416 [URL<\/a>]<\/p>\n\n\n\n

S. Karman, F. Tesolin, A. Dago, M. Mercandelli, C. Samori and S. Levantino, “A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability<\/strong>,” 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)<\/em>, Atlanta, GA, USA, 2021, pp. 67-70. doi: 10.1109\/RFIC51843.2021.9490476 [URL]<\/a><\/p>\n\n\n\n

A. Santiccioli et al<\/em>., “32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays,<\/strong>” 2021 IEEE International Solid- State Circuits Conference (ISSCC)<\/em>, San Francisco, CA, USA, 2021, pp. 456-458. doi: 10.1109\/ISSCC42613.2021.9365972 [URL<\/a>]<\/p>\n\n\n\n

M. Mercandelli et al<\/em>., “32.3 A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter<\/strong>,” 2021 IEEE International Solid- State Circuits Conference (ISSCC)<\/em>, San Francisco, CA, USA, 2021, pp. 445-447. doi: 10.1109\/ISSCC42613.2021.9365768 [URL<\/a>]<\/p>\n\n\n\n

A. Garghetti, A. L. Lacaita, D. Seebacher, M. Bassi and S. Levantino, “A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS<\/strong>,” 2021 IEEE Custom Integrated Circuits Conference (CICC)<\/em>, Austin, TX, USA, 2021, pp. 1-2. doi: 10.1109\/CICC51472.2021.9431565 [URL<\/a>]<\/p>\n\n\n\n

L. Avallone, M. Mercandelli, A. Santiccioli, M. P. Kennedy, S. Levantino and C. Samori, “A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs,<\/strong>” in IEEE Transactions on Circuits and Systems I: Regular Papers<\/em>, vol. 68, no. 7, pp. 2775-2786, July 2021. doi: 10.1109\/TCSI.2021.3072344 [URL<\/a>]<\/p>\n\n\n\n

S. Karman, F. Tesolin, S. Levantino and C. Samori, “A Novel Topology of Coupled Phase-Locked Loops,<\/strong>” in IEEE Transactions on Circuits and Systems I: Regular Papers<\/em>, vol. 68, no. 3, pp. 989-997, March 2021. doi: 10.1109\/TCSI.2020.3043466 [URL<\/a>]<\/p>\n\n\n\n

2020<\/h2>\n\n\n\n

M. Leoncini, S. Levantino, and M. Ghioni, “Design issues and performance analysis of CCM boost converters with RHP zero mitigation via inductor current sensing<\/strong>“, Journal of Power Electronics, vol. 21, no. 2, pp. 285-295. [URL]<\/a><\/p>\n\n\n\n

T. Rosa, M. Leoncini and S. L. M. Ghioni, “A Novel Start-Up Technique for Time-Based Boost Converters with Seamless PFM\/PWM Transition<\/strong>,” 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-5, doi: 10.1109\/ISCAS45731.2020.9180418. [URL]<\/a><\/p>\n\n\n\n

A. Santiccioli et al<\/em>., “A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang\u2013Bang PLL With Digital Frequency-Error Recovery for Fast Locking,<\/strong>” in IEEE Journal of Solid-State Circuits<\/em>, vol. 55, no. 12, pp. 3349-3361, Dec. 2020. doi: 10.1109\/JSSC.2020.3019344 [URL<\/a>]<\/p>\n\n\n\n

D. Cherniak et al<\/em>., “A 250-Mb\/s Direct Phase Modulator With \u221242.<\/strong>4-dB EVM Based on a 14-GHz Digital PLL,” in IEEE Solid-State Circuits Letters<\/em>, vol. 3, pp. 126-129, 2020. doi: 10.1109\/LSSC.2020.3006519 [URL<\/a>]<\/p>\n\n\n\n

A. Santiccioli et al<\/em>., “17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking,<\/strong>” 2020 IEEE International Solid- State Circuits Conference – (ISSCC)<\/em>, San Francisco, CA, USA, 2020, pp. 268-270. doi: 10.1109\/ISSCC19947.2020.9063094 [URL<\/a>]<\/p>\n\n\n\n

M. Mercandelli et al<\/em>., “17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter,<\/strong>” 2020 IEEE International Solid- State Circuits Conference – (ISSCC)<\/em>, San Francisco, CA, USA, 2020, pp. 274-276. doi: 10.1109\/ISSCC19947.2020.9063135 [URL<\/a>]<\/p>\n\n\n\n

L. Avallone, M. P. Kennedy, S. Karman, C. Samori and S. Levantino, “Jitter Minimization in Digital PLLs with Mid-Rise TDCs,<\/strong>” in IEEE Transactions on Circuits and Systems I: Regular Papers<\/em>, vol. 67, no. 3, pp. 743-752, March 2020. doi: 10.1109\/TCSI.2019.2959252[URL<\/a>]<\/p>\n\n\n\n

2019<\/h2>\n\n\n\n

A. Santiccioli, M. Mercandelli, A. L. Lacaita, C. Samori and S. Levantino, “A 1.6-to-3.0-GHz<\/strong> Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power<\/strong>,” in IEEE Journal of Solid-State Circuits<\/em>, vol. 54, no. 11, pp. 3149-3160, Nov. 2019. doi: 10.1109\/JSSC.2019.2941259 [URL]<\/a><\/p>\n\n\n\n

L. Bertulessi et al<\/em>., “A 30-GHz Digital Sub-Sampling Fractional-N PLL With \u2212238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS<\/strong>,” in IEEE Journal of Solid-State Circuits<\/em>, vol. 54, no. 12, pp. 3493-3502, Dec. 2019. doi: 10.1109\/JSSC.2019.2940332 [URL]<\/a><\/p>\n\n\n\n

A. Santiccioli, M. Mercandelli, A. L. Lacaita, C. Samori and S. Levantino, “A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power<\/strong>,” 2019 IEEE Custom Integrated Circuits Conference (CICC)<\/em>, Austin, TX, USA, 2019, pp. 1-4. doi: 10.1109\/CICC.2019.8780235[URL]<\/a><\/p>\n\n\n\n

D. Cherniak, C. Samori and S. Levantino, “Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS : (Invited Paper)<\/strong>,” 2019 IEEE Custom Integrated Circuits Conference (CICC)<\/em>, Austin, TX, USA, 2019, pp. 1-8. doi: 10.1109\/CICC.2019.8780146 [URL]<\/a><\/p>\n\n\n\n

A. Santiccioli, C. Samori, A. L. Lacaita and S. Levantino, “Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops<\/strong>,” in IEEE Transactions on Circuits and Systems I: Regular Papers<\/em>, vol. 66, no. 10, pp. 3775-3785, Oct. 2019. doi: 10.1109\/TCSI.2019.2918027 [URL]<\/a><\/p>\n\n\n\n

L. Grimaldi et al<\/em>., “16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS<\/strong>,” 2019 IEEE International Solid- State Circuits Conference – (ISSCC)<\/em>, San Francisco, CA, USA, 2019, pp. 268-270. doi: 10.1109\/ISSCC.2019.8662411 [URL]<\/a><\/p>\n\n\n\n

A. Garghetti, A. L. Lacaita and S. Levantino, “A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking,<\/strong>” in IEEE Transactions on Circuits and Systems I: Regular Papers<\/em>, vol. 66, no. 5, pp. 1737-1745, May 2019. doi: 10.1109\/TCSI.2018.2871178 [URL]<\/a><\/p>\n\n\n\n

2018<\/h2>\n\n\n\n

…<\/p>\n\n\n\n

2017<\/h2>\n\n\n\n

2016<\/h2>\n\n\n\n

2015<\/h2>\n\n\n\n

<\/p>\n","protected":false},"excerpt":{"rendered":"

2026 … 2025 I. Ferrari, G. Zanoletti, L. Bertulessi, A. L. Lacaita, C. Samori and A. Bonfanti, “An Analysis of Switch Thermal Noise in SAR Converters,” in IEEE Transactions on Circuits and Systems II: Express Briefs, doi: 10.1109\/TCSII.2025.3622315. A. Ceroni, G. … Continue reading →<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"parent":0,"menu_order":4,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-11","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/arplab.deib.polimi.it\/index.php?rest_route=\/wp\/v2\/pages\/11","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/arplab.deib.polimi.it\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/arplab.deib.polimi.it\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/arplab.deib.polimi.it\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/arplab.deib.polimi.it\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=11"}],"version-history":[{"count":28,"href":"https:\/\/arplab.deib.polimi.it\/index.php?rest_route=\/wp\/v2\/pages\/11\/revisions"}],"predecessor-version":[{"id":675,"href":"https:\/\/arplab.deib.polimi.it\/index.php?rest_route=\/wp\/v2\/pages\/11\/revisions\/675"}],"wp:attachment":[{"href":"https:\/\/arplab.deib.polimi.it\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=11"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}